LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2018-10-20	123bcb3 Browse files » allwinner: Introduce names for SoC IDs ... We will soon make more use of the Allwinner SoC ID, to differentiate the platform setup. Introduce definitions to avoid dealing with magic numbers and make the code more readable. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 20 Oct 2018
	f78f00a Browse files » allwinner: H6: Fix SRAM size ... The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part ending at 0x117fff (although with gaps in between). So SUNXI_SRAM_SIZE should be 0xf8000, not 0x98000. Fix this to map the arisc exception vector area, which we will need shortly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 20 Oct 2018
	4306051 Browse files » allwinner: Disable USE_COHERENT_MEM ... According to the documentation, platforms may choose to trade memory footprint for performance (and elegancy) by not providing a separately mapped coherent page. Since a debug build is getting close to the SRAM size limit already, this allows us to save about 3.5KB of BSS and have some room for future enhancements. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 20 Oct 2018
	c3af6b0 Browse files » allwinner: Adjust memory mapping to fit into 256MB ... At the moment we map as much of the DRAM into EL3 as possible, however we actually don't use it. The only exception is the secure DRAM for BL32 (if that is configured). To decrease the memory footprint of ATF, we save on some page tables by reducing the memory mapping to the actually required regions: SRAM, device MMIO, secure DRAM and U-Boot (to be used later). This introduces a non-identity mapping for the DRAM regions. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 20 Oct 2018
	a80490c Browse files » allwinner: Unify platform.mk files ... For the two different platforms we support in the Allwinner port we mostly rely on header files covering the differences. This leads to the platform.mk files in the respective directories to be almost identical. To avoid further divergence and make sure that one platform doesn't break accidentally, let's create a shared allwinner-common.mk file and include that from the platform directory. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 20 Oct 2018
2018-10-18	Unverified 0595abc Browse files » Merge pull request #1632 from Yann-lms/stm32mp1_mmc ... Add MMC support for STM32MP1 Soby Mathew authored on 18 Oct 2018 GitHub committed on 18 Oct 2018
	Unverified a51443f Browse files » Merge pull request #1582 from ldts/rcar_gen3/upstream ... rcar_gen3: initial support Soby Mathew authored on 18 Oct 2018 GitHub committed on 18 Oct 2018
	Unverified 0059be2 Browse files » Merge pull request #1553 from glneo/dcache-late-disable ... Allow D-Cache to remain on during core power-down Soby Mathew authored on 18 Oct 2018 GitHub committed on 18 Oct 2018
	Unverified 97f1233 Browse files » Merge pull request #1629 from robertovargas-arm/hw-assisted-coherency-lock ... Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled Soby Mathew authored on 18 Oct 2018 GitHub committed on 18 Oct 2018
	Unverified 1278f36 Browse files » Merge pull request #1631 from deepan02/deepak-arm/relocate-jump_if_cpu_midr ... plat/arm: relocate the jump_if_cpu_midr macro. Soby Mathew authored on 18 Oct 2018 GitHub committed on 18 Oct 2018
	Unverified 7be05cd Browse files » Merge pull request #1628 from antonio-nino-diaz-arm/an/sharing ... plat/arm: Small reorganization of platform code Soby Mathew authored on 18 Oct 2018 GitHub committed on 18 Oct 2018
2018-10-17	84433c5 Browse files » rcar_gen3: drivers: watchdog ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	33947f2 Browse files » rcar_gen3: drivers: serial controller interface ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	b3bd073 Browse files » rcar_gen3: drivers: spi multio bus controller ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	0709efb Browse files » rcar_gen3: drivers: rom api ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	32c70e4 Browse files » rcar_gen3: drivers: power controller ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	0a106e2 Browse files » rcar_gen3: drivers: console ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	c2f2868 Browse files » rcar_gen3: drivers: io [emmc/mem] ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	da963e3 Browse files » rcar_gen3: drivers: i2c dvfs ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	3bfe202 Browse files » rcar_gen3: drivers: emmc ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	2f7de72 Browse files » rcar_gen3: drivers: dma ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	d427fc9 Browse files » rcar_gen3: drivers: micro delay generator ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	3a81abb Browse files » rcar_gen3: drivers: cpld ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	070b0f0 Browse files » rcar_gen3: drivers: board identification ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	0cdb86d Browse files » rcar_gen3: drivers: avs [adaptive voltage scaling] ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	2f473cc Browse files » rcar_gen3: drivers: authentication ... Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	6ac2892 Browse files » rcar_gen3: drivers: staging ... - ddr - pfc [pin function controller] - qos [bandwidth] checkpatch.pl is generating too many errors. Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
	7e532c4 Browse files » rcar-gen3: initial commit for the rcar-gen3 boards ... Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com> Jorge Ramirez-Ortiz authored on 23 Sep 2018 ldts committed on 17 Oct 2018
2018-10-16	6a655a8 Browse files » ti: k3: common: Do not disable cache on TI K3 core powerdown ... Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com> Andrew F. Davis committed on 16 Oct 2018
2018-10-16	32aee84 Browse files » scmi: Optimize bakery locks when HW_ASSISTED_COHERENCY is enabled ... When HW_ASSISTED_COHERENCY is enabled we can use spinlocks instead of using the more complex and slower bakery algorithm. Change-Id: I9d791a70050d599241169b9160a67e57d5506564 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com> Roberto Vargas committed on 16 Oct 2018