intel: Enable bridge access in Intel platform ...

Add bridge enablement features for each platform.
The bridge access will be enabled automatically for FPGA 1st
configuration only.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I264757b257a209e1c3c4206660f21c5d67af0d2f

intel: Modify non secure access function ...

Combine both peripheral and bridge non-secure access code
into a single callable function

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I38d335ed8d1e9f55d337b63cca121a473897ef70

Merge "plat: intel: Fix UEFI decompression issue" into integration

Merge "intel: Change all global sip function to static" into integration

plat: intel: Fix UEFI decompression issue ...

UEFI decompression will fail if the payload size is too large and the load
address is too low. This patch moves the payload to a higher address to fix
the issue

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Change-Id: I36087fbd2237b62891c59dbe2d34336bddfaa396

intel: Change all global sip function to static ...

All function in socfpga_sip_svc.c should only be called locally except
sip_smc_handler().

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib84ef9a2e521967baa4cfd32e6bc569dd3a5d2f5

Merge "a8k: Implement platform specific power off" into integration

Merge "allwinner: Reenable USE_COHERENT_MEM" into integration

allwinner: Reenable USE_COHERENT_MEM ...

Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies the code, this is a beneficial change for
loaded image (.text) size, where we are still close to the size limit.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9

a8k: Implement platform specific power off ...

Implements a way to add platform specific power off code to a
Marvell Armada 8K platform.

Marvell Armada 8K boards can now add a board/system_power.c file
that contains a system_power_off() function.
This function can now send a command to a power management MCU or
other board periferals before shutting the board down.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db
---
I am working on a device that will be ported later, which has a
custom power management MCU that handles LEDs, board power and fans
and requires this separation.

Merge changes from topic "sip-svc" into integration ...

* changes:
  intel: Implement platform specific system reset 2
  intel: Enable SiP SMC secure register access

Merge "uniphier: call uniphier_scp_is_running() only when on-chip STM is supported" into integration

Merge "intel: Fix memory calibration" into integration

Merge "rpi4: Fix documentation of armstub config entry" into integration

rpi4: Fix documentation of armstub config entry ...

It's in fact mandatory. Seen with RPi firmware 1.20190925.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892

Merge "plat: rpi4: Skip UART initialisation" into integration

Merge "console: 16550: Prepare for skipping initialisation" into integration

Merge changes from topic "add-versal-soc-support" into integration ...

* changes:
  zynqmp: pm: Add LPD WDT clock to the pm_clock structure
  zynqmp: pm: Fix clock models and IDs of GEM-related clocks
  zynqmp: pm: Rename FPD WDT clock ID
  plat: xilinx: zynqmp: Correct syscnt freq for QEMU
  arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
  arm64: zynqmp: Add id for new RFSoC device ZU39DR

Merge "allwinner: Move the NOBITS region to SRAM A1" into integration

Merge "intel: Remove un-needed checks for qspi driver r/w" into integration

Merge changes from topic "tegra-misra-21.1-fixes" into integration ...

* changes:
  Tegra194: drivers: fix violations of MISRA Rule 21.1
  Tegra: include: fix violations of MISRA Rule 21.1

Merge "docs: GCC toolchain upgrade to version 9.2-2019.12" into integration

intel: Remove un-needed checks for qspi driver r/w ...

This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53

Tegra194: drivers: fix violations of MISRA Rule 21.1 ...

This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc

Tegra: include: fix violations of MISRA Rule 21.1 ...

This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185

docs: GCC toolchain upgrade to version 9.2-2019.12 ...

This toolchain provides multiple cross compilers and are publicly
available on developer.arm.com

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I910200174d5bad985504d1af4a1ae5819b524003
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "Unify type of "cpu_idx" across PSCI module." into integration

Unify type of "cpu_idx" across PSCI module. ...

NOTE for platform integrators:
   API `plat_psci_stat_get_residency()` third argument
   `last_cpu_idx` is changed from "signed int" to the
   "unsigned int" type.

Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.

2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent

Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.

Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c

Merge "rcar_gen3: plat: Pass DT to OpTee OS" into integration

Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration