LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-10-28	3ed5606 Browse files » Use constant stack size with RECLAIM_INIT_CODE ... Currently, when RECLAIM_INIT_CODE is set, the stacks are scaled to ensure that the entirety of the init section can be reclaimed as stack. This causes an issue in lib/psci/aarch64/psci_helpers.S, where the stack size is used for cache operations in psci_do_pwrdown_cache_maintenance(). If the stacks are scaled, then the PSCI code may fail to invalidate some of the stack memory before power down. Resizing stacks is also not good for stability in general, since code that works with a small number of cores may overflow the stack when the number of cores is increased. Change to make every stack be PLATFORM_STACK_SIZE big, and allow the total stack to be smaller than the init section. Any pages of the init section not reclaimed as stack will be set to read-only and execute-never, for security. Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8 Signed-off-by: David Horstmann <david.horstmann@arm.com> David Horstmann committed on 28 Oct 2020
2020-10-12	7ad3981 Browse files » Merge "mediatek: mt8192: add GIC600 support" into integration Manish Pandey authored on 12 Oct 2020 TrustedFirmware Code Review committed on 12 Oct 2020
2020-10-09	7d3a7ec Browse files » Merge "Workaround for Cortex A77 erratum 1925769" into integration Lauren Wehrmeister authored on 9 Oct 2020 TrustedFirmware Code Review committed on 9 Oct 2020
	f224d3c Browse files » Merge "drivers: stm32_fmc2_nand: fix incorrect error detection" into integration Manish Pandey authored on 9 Oct 2020 TrustedFirmware Code Review committed on 9 Oct 2020
	210ac18 Browse files » Merge changes I99a5d96f,I89b950f0 into integration ... * changes: lib/cpus: update MIDR value for rainier cpu fdts: enable virtio-rng component for morello fvp platform Manish Pandey authored on 9 Oct 2020 TrustedFirmware Code Review committed on 9 Oct 2020
	3e0a861 Browse files » lib/cpus: update MIDR value for rainier cpu ... This patch updates the MIDR value for rainier cpu. Change-Id: I99a5d96f757239cf65b2688095c4ec66cd991cf9 Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Jagadeesh Ujja authored on 7 Oct 2020 jagadeesh.ujja committed on 9 Oct 2020
	eff2ede Browse files » Merge changes from topic "stm32mp1_platform_mk" into integration ... * changes: stm32mp1: cosmetics in platform.mk stm32mp1: update rules for stm32image tool stm32mp1: add macros to define PLAT_PARTITION_MAX_ENTRIES stm32mp1: sort platform.mk stm32mp1: use ASFLAGS for binary paths stm32mp1: use internal MAKE_LD macro to generate stm32 linker files Manish Pandey authored on 9 Oct 2020 TrustedFirmware Code Review committed on 9 Oct 2020
	38b2304 Browse files » stm32mp1: cosmetics in platform.mk ... Remove some useless extra tabs or spaces. Replace some spaces with tabs. Change-Id: I0e8e2a1a1be7a1109ba7f3e3ae35e3fe1b5b4552 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 18 Sep 2020 Manish Pandey committed on 9 Oct 2020
	128e0b3 Browse files » stm32mp1: update rules for stm32image tool ... In heavy parallel builds, it has sometimes been seen issues with the tool not generated before it was needed. Change some rules order and dependency to solve that. Change-Id: I8f4b4f46a2ea0fe496bc66bca47c66d1c81d3c99 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 18 Sep 2020 Manish Pandey committed on 9 Oct 2020
	3e0727d Browse files » stm32mp1: add macros to define PLAT_PARTITION_MAX_ENTRIES ... There were fixed values when computing PLAT_PARTITION_MAX_ENTRIES. Use STM32_BL33_PARTS_NUM and STM32_RUNTIME_PARTS_NUM. The first one is for the number of copies of BL33. The second one depends on the use case SP_min or OP-TEE. For OP-TEE, there are 3 partitions. For SP_min, as it is in the same binary as BL2, it is set to 0. It will be set to 1 if BL32 is in a separate binary. Change-Id: Iba4d8ec5fbc713bebfbdcd9f9426c3fded20d3ad Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 17 Sep 2020 Manish Pandey committed on 9 Oct 2020
	2eaffd5 Browse files » stm32mp1: sort platform.mk ... First put Makefile variables definition, then definitions for each feature, then C flags, then source files, then compilation rules. Change-Id: I238115ea2fe4ebafccd2135979814c27932c34e2 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 12 Feb 2020 Manish Pandey committed on 9 Oct 2020
	49e2373 Browse files » stm32mp1: use ASFLAGS for binary paths ... To simplify the rule that creates the concatenated binary, use ASFLAGS instead of adding all paths in the AS command line. This allows a better management if a binary is not present. Change-Id: Ic8b4566e7dedc6f55be355a92e3b214cef138d9b Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 23 Jan 2020 Manish Pandey committed on 9 Oct 2020
	276a9c1 Browse files » stm32mp1: use internal MAKE_LD macro to generate stm32 linker files ... The previous proprietary version was not correctly handling dependencies. Using MAKE_LD from make_helpers files now correctly handles that. The generated linker script is the same as before. Change-Id: Iccfd8dc3fffa7a33e73b184b72e0dfd5d26bc9c9 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 14 May 2020 Manish Pandey committed on 9 Oct 2020
2020-10-08	390181a Browse files » fdts: enable virtio-rng component for morello fvp platform ... enable virtio-rng component for morello fvp platform Change-Id: I89b950f067a4d14dfa418de3859c88c8f91cf7c5 Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Jagadeesh Ujja committed on 8 Oct 2020
2020-10-08	4496600 Browse files » drivers: stm32_fmc2_nand: fix incorrect error detection ... Clear interrupt flag register after each sector read to avoid issue when checking the register status. Without clearing the interrupt, the status read doesn't wait properly the ready bit. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: If290e3f165b986f0e736bb1b5e4d3dad4b749d74 Lionel Debieve committed on 8 Oct 2020
2020-10-07	35c7537 Browse files » Workaround for Cortex A77 erratum 1925769 ... Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9 johpow01 authored on 10 Sep 2020 John Powell committed on 7 Oct 2020
	bb68a9d Browse files » Merge "fdt: Fix coverity complaint about 32-bit multiplication" into integration Madhukar Pappireddy authored on 7 Oct 2020 TrustedFirmware Code Review committed on 7 Oct 2020
	4276cfe Browse files » fdt: Fix coverity complaint about 32-bit multiplication ... Coverity raised an eyebrow over our GICR frame size calculation: ======== CID 362942: Integer handling issues (OVERFLOW_BEFORE_WIDEN) Potentially overflowing expression "nr_cores * gicr_frame_size" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). ======== Even with a GICv4 (256KB frame size) we need 16384 cores to overflow 32-bit, so it's not a practical issue. But it's also easy to fix, so let's just do that: cast gicr_frame_size to an unsigned 64-bit integer, so that the multiplication is done in the 64-bit realm. Change-Id: Iad10e19b9e58d5fbf9d13205fbcef0aac5ae48af Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 7 Oct 2020
2020-10-06	a4fdb89 Browse files » Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration ... * changes: Rename Neoverse Zeus to Neoverse V1 Rename Cortex Hercules AE to Cortex 78 AE Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
	b8f8457 Browse files » Merge "plat/arm: common: add guard for arm_get_rotpk_info_regs" into integration Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
	3fad996 Browse files » Merge "doc: Update list of supported FVP platforms" into integration Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
	3bfcc9d Browse files » plat/arm: common: add guard for arm_get_rotpk_info_regs ... Only define arm_get_rotpk_info_regs if ROTPK is in registers, i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will allow platform build without definition of TZ_PUB_KEY_HASH_BASE if dedicated registers for ROTPK are not available on the platform. Change-Id: I74ee2d5007f5d876a031a1efca20ebee2dede0c7 Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif authored on 5 Oct 2020 Alexei Fedorov committed on 6 Oct 2020
	eeb77da Browse files » Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration ... * changes: docs: marvell: update mv_ddr branch plat: marvell: armada: a3k: rename the UART images archive plat: marvell: armada: a3k: allow image load to RAM address 0 marvell: comphy: cp110: add support for USB comphy polarity invert marvell: comphy: cp110: add support for SATA comphy polarity invert marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353 drivers: marvell: mochi: Update AP incoming masters secure level plat: marvell: armada: add ccu window for workaround errata-id 3033912 plat: marvell: ap806: implement workaround for errata-id FE-4265711 Manish Pandey authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
2020-10-05	f8dee97 Browse files » Merge "Workaround for Cortex A76 erratum 1868343" into integration Madhukar Pappireddy authored on 5 Oct 2020 TrustedFirmware Code Review committed on 5 Oct 2020
	467937b Browse files » Rename Neoverse Zeus to Neoverse V1 ... Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
	5effe0b Browse files » Rename Cortex Hercules AE to Cortex 78 AE ... Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
2020-10-04	5ecfd89 Browse files » Merge "doc: stm32mp1: Improve OP-TEE related documentation" into integration Madhukar Pappireddy authored on 4 Oct 2020 TrustedFirmware Code Review committed on 4 Oct 2020
	1d935a1 Browse files » docs: marvell: update mv_ddr branch ... Now that the BLE image sources (mv_ddr) are updated, reflect the proper branch in the Armada build howto. Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 4 Oct 2020
	fc8dc49 Browse files » plat: marvell: armada: a3k: rename the UART images archive ... Add *.bin extension to UART recovery images archive name. Such naming will cause the UART recovery images to be copied to the Buildroot output folder upon flash image build. Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 24 Oct 2019 Marcin Wojtas committed on 4 Oct 2020
	270367f Browse files » plat: marvell: armada: a3k: allow image load to RAM address 0 ... Marvell uses RAM address 0x0 for loading BL33 stage images. When ATF is built with DEBUG=1, its IO subsystem fails on assert checking the destination RAM address != 0. This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform allowing to bypass the above check in debug mode. Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 27 Aug 2019 Marcin Wojtas committed on 4 Oct 2020