LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-10-06	3fad996 Browse files » Merge "doc: Update list of supported FVP platforms" into integration Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
2020-10-06	eeb77da Browse files » Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration ... * changes: docs: marvell: update mv_ddr branch plat: marvell: armada: a3k: rename the UART images archive plat: marvell: armada: a3k: allow image load to RAM address 0 marvell: comphy: cp110: add support for USB comphy polarity invert marvell: comphy: cp110: add support for SATA comphy polarity invert marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353 drivers: marvell: mochi: Update AP incoming masters secure level plat: marvell: armada: add ccu window for workaround errata-id 3033912 plat: marvell: ap806: implement workaround for errata-id FE-4265711 Manish Pandey authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
2020-10-05	f8dee97 Browse files » Merge "Workaround for Cortex A76 erratum 1868343" into integration Madhukar Pappireddy authored on 5 Oct 2020 TrustedFirmware Code Review committed on 5 Oct 2020
2020-10-04	5ecfd89 Browse files » Merge "doc: stm32mp1: Improve OP-TEE related documentation" into integration Madhukar Pappireddy authored on 4 Oct 2020 TrustedFirmware Code Review committed on 4 Oct 2020
	1d935a1 Browse files » docs: marvell: update mv_ddr branch ... Now that the BLE image sources (mv_ddr) are updated, reflect the proper branch in the Armada build howto. Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 4 Oct 2020
	fc8dc49 Browse files » plat: marvell: armada: a3k: rename the UART images archive ... Add *.bin extension to UART recovery images archive name. Such naming will cause the UART recovery images to be copied to the Buildroot output folder upon flash image build. Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 24 Oct 2019 Marcin Wojtas committed on 4 Oct 2020
	270367f Browse files » plat: marvell: armada: a3k: allow image load to RAM address 0 ... Marvell uses RAM address 0x0 for loading BL33 stage images. When ATF is built with DEBUG=1, its IO subsystem fails on assert checking the destination RAM address != 0. This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform allowing to bypass the above check in debug mode. Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 27 Aug 2019 Marcin Wojtas committed on 4 Oct 2020
	ff9cfdc Browse files » marvell: comphy: cp110: add support for USB comphy polarity invert ... The polarity inversion for USB was not tested due to lack of hw design which requires it. Currently all supported boards doesn't require USB phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Enable the option for the ones that need it. Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	38f6dac Browse files » marvell: comphy: cp110: add support for SATA comphy polarity invert ... The cp110 comphy has ability to invert RX and/or TX polarity. Polarity depends on board design. Currently all supported boards doesn't require SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	8fa1340 Browse files » marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353 ... According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should be toggled in addition to the XFI/SFI PHY reset. Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 4 Oct 2020
	11e6ed0 Browse files » drivers: marvell: mochi: Update AP incoming masters secure level ... Do not force non-secure access level for PIDI masters when LLC_SRAM is enabled. The EIP197 is located on CP0 and need to access secure SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not changed when forwarded to address decoding tables. Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 22 Aug 2019 Marcin Wojtas committed on 4 Oct 2020
	a9688f0 Browse files » plat: marvell: armada: add ccu window for workaround errata-id 3033912 ... Added ccu window to allow access to addresses in the range [0xf100_0000, 0xf1ff_ffff]. Change-Id: I63ee68338d674114d01cd627198dc907653493e8 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 25 Dec 2019 Marcin Wojtas committed on 4 Oct 2020
	6792ba1 Browse files » plat: marvell: ap806: implement workaround for errata-id FE-4265711 ... ERRATA ID: FE-4265711 - Incorrect CNTVAL reading CNTVAL reflects the global system counter value in binary format. Due to this erratum, the CNTVAL value presented to the processor may be incorrect for several clock cycles. Workaround: Override the default value of AP Register Device General control 20 [19:16] and AP Register Device General Control 21 [11:8] to the value of 0x3. Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Stefan Chulski authored on 24 Jun 2019 Marcin Wojtas committed on 4 Oct 2020
2020-10-03	2539dd3 Browse files » Merge "libfdt: Upgrade libfdt source files" into integration Alexei Fedorov authored on 3 Oct 2020 TrustedFirmware Code Review committed on 3 Oct 2020
	c2c03e7 Browse files » Merge "spmd: Fix signedness comparison warning" into integration Alexei Fedorov authored on 3 Oct 2020 TrustedFirmware Code Review committed on 3 Oct 2020
	55ff05f Browse files » Workaround for Cortex A76 erratum 1868343 ... Cortex A76 erratum 1868343 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call. SDEN can be found here: https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d johpow01 authored on 29 Sep 2020 Alexei Fedorov committed on 3 Oct 2020
2020-10-02	950e37d Browse files » Merge "morello: Add Morello platform documentation" into integration Madhukar Pappireddy authored on 2 Oct 2020 TrustedFirmware Code Review committed on 2 Oct 2020
	dc57bea Browse files » Merge "fdts: stm32mp1: realign device tree with kernel" into integration Madhukar Pappireddy authored on 2 Oct 2020 TrustedFirmware Code Review committed on 2 Oct 2020
	3b45666 Browse files » libfdt: Upgrade libfdt source files ... Update the libfdt source files, the upstream commit is 73e0f143b73d ("libfdt: fdt_strerror(): Fix comparison warning"). This brings us the fixes for the signed/unsigned comparison warnings, so platforms can enable -Wsign-compare now. Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara authored on 1 Oct 2020 Alexei Fedorov committed on 2 Oct 2020
	6e4da01 Browse files » spmd: Fix signedness comparison warning ... With -Wsign-compare, compilers issue a warning in the SPMD code: ==================== services/std_svc/spmd/spmd_pm.c:35:22: error: comparison of integer expressions of different signedness: 'int' and 'unsigned int' [-Werror=sign-compare] 35 \| if ((id < 0) \|\| (id >= PLATFORM_CORE_COUNT)) { \| ^~ cc1: all warnings being treated as errors ==================== Since we just established that "id" is positive, we can safely cast it to an unsigned type to make the comparison have matching types. Change-Id: I6ef24804c88136d7e3f15de008e4fea854f10ffe Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara authored on 2 Oct 2020 Alexei Fedorov committed on 2 Oct 2020
	14bac44 Browse files » Merge "morello: Add changes to fix build of Morello Platform" into integration Alexei Fedorov authored on 2 Oct 2020 TrustedFirmware Code Review committed on 2 Oct 2020
	8445253 Browse files » morello: Add Morello platform documentation ... Morello platform has a SCP which brings the primary Rainier CPU out of reset which starts executing at BL31. This patch provides documentation support for Morello platform. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2 Chandni Cherukuri authored on 1 Oct 2020 chandni cherukuri committed on 2 Oct 2020
	ccf220a Browse files » doc: Update list of supported FVP platforms ... Updated the list of supported FVP platform as per latest FVP platform release. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a Manish V Badarkhe committed on 2 Oct 2020
	219e45c Browse files » doc: stm32mp1: Improve OP-TEE related documentation ... stm32mp15_optee_defconfig has been dropped from U-Boot as it became identical to stm32mp15_trusted_defconfig. Furthermore give a hint how OP-TEE is supposed to be installed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213 Jan Kiszka committed on 2 Oct 2020
	6c07a92 Browse files » morello: Add changes to fix build of Morello Platform ... This patch makes changes required to get the morello platform working with the tip of TF-A. Change-Id: I095006615c9959bba49fcc75b52e1de7d7486309 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Chandni Cherukuri committed on 2 Oct 2020
2020-10-01	fa417e6 Browse files » Merge "Measured Boot Driver: Fix MISRA-C 2012 defects" into integration Madhukar Pappireddy authored on 1 Oct 2020 TrustedFirmware Code Review committed on 1 Oct 2020
	82f38d5 Browse files » Merge "Crypto library: Migrate support to MbedTLS v2.24.0" into integration Olivier Deprez authored on 1 Oct 2020 TrustedFirmware Code Review committed on 1 Oct 2020
	ea14b51 Browse files » Crypto library: Migrate support to MbedTLS v2.24.0 ... This patch migrates the mbedcrypto dependency for TF-A to mbedTLS repo v2.24.0 which is the latest release tag. The relevant documentation is updated to reflect the use of new version. Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 1 Oct 2020
2020-09-30	428518c Browse files » Merge changes from topic "stm32_exceptions" into integration ... * changes: stm32mp1: correct crash console GPIO alternate configuration stm32mp1: add plat_panic_handler function stm32mp1: update plat_report_exception Align AARCH32 version of debug.S with AARCH64 Manish Pandey authored on 30 Sep 2020 TrustedFirmware Code Review committed on 30 Sep 2020
2020-09-29	2173b3e Browse files » Merge changes from topic "fpga_generic" into integration ... * changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add devicetree file arm_fpga: Remove SPE PMU DT node if SPE is not available arm_fpga: Adjust GICR size in DT to match number of cores fdt: Add function to adjust GICv3 redistributor size drivers: arm: gicv3: Allow detecting number of cores André Przywara authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020