LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-10-08	4496600 Browse files » drivers: stm32_fmc2_nand: fix incorrect error detection ... Clear interrupt flag register after each sector read to avoid issue when checking the register status. Without clearing the interrupt, the status read doesn't wait properly the ready bit. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: If290e3f165b986f0e736bb1b5e4d3dad4b749d74 Lionel Debieve committed on 8 Oct 2020
2020-10-07	bb68a9d Browse files » Merge "fdt: Fix coverity complaint about 32-bit multiplication" into integration Madhukar Pappireddy authored on 7 Oct 2020 TrustedFirmware Code Review committed on 7 Oct 2020
2020-10-07	4276cfe Browse files » fdt: Fix coverity complaint about 32-bit multiplication ... Coverity raised an eyebrow over our GICR frame size calculation: ======== CID 362942: Integer handling issues (OVERFLOW_BEFORE_WIDEN) Potentially overflowing expression "nr_cores * gicr_frame_size" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). ======== Even with a GICv4 (256KB frame size) we need 16384 cores to overflow 32-bit, so it's not a practical issue. But it's also easy to fix, so let's just do that: cast gicr_frame_size to an unsigned 64-bit integer, so that the multiplication is done in the 64-bit realm. Change-Id: Iad10e19b9e58d5fbf9d13205fbcef0aac5ae48af Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 7 Oct 2020
2020-10-06	a4fdb89 Browse files » Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration ... * changes: Rename Neoverse Zeus to Neoverse V1 Rename Cortex Hercules AE to Cortex 78 AE Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
	b8f8457 Browse files » Merge "plat/arm: common: add guard for arm_get_rotpk_info_regs" into integration Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
	3fad996 Browse files » Merge "doc: Update list of supported FVP platforms" into integration Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
	3bfcc9d Browse files » plat/arm: common: add guard for arm_get_rotpk_info_regs ... Only define arm_get_rotpk_info_regs if ROTPK is in registers, i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will allow platform build without definition of TZ_PUB_KEY_HASH_BASE if dedicated registers for ROTPK are not available on the platform. Change-Id: I74ee2d5007f5d876a031a1efca20ebee2dede0c7 Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif authored on 5 Oct 2020 Alexei Fedorov committed on 6 Oct 2020
	eeb77da Browse files » Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration ... * changes: docs: marvell: update mv_ddr branch plat: marvell: armada: a3k: rename the UART images archive plat: marvell: armada: a3k: allow image load to RAM address 0 marvell: comphy: cp110: add support for USB comphy polarity invert marvell: comphy: cp110: add support for SATA comphy polarity invert marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353 drivers: marvell: mochi: Update AP incoming masters secure level plat: marvell: armada: add ccu window for workaround errata-id 3033912 plat: marvell: ap806: implement workaround for errata-id FE-4265711 Manish Pandey authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
2020-10-05	f8dee97 Browse files » Merge "Workaround for Cortex A76 erratum 1868343" into integration Madhukar Pappireddy authored on 5 Oct 2020 TrustedFirmware Code Review committed on 5 Oct 2020
	467937b Browse files » Rename Neoverse Zeus to Neoverse V1 ... Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
	5effe0b Browse files » Rename Cortex Hercules AE to Cortex 78 AE ... Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 30 Sep 2020 Madhukar Pappireddy committed on 5 Oct 2020
2020-10-04	5ecfd89 Browse files » Merge "doc: stm32mp1: Improve OP-TEE related documentation" into integration Madhukar Pappireddy authored on 4 Oct 2020 TrustedFirmware Code Review committed on 4 Oct 2020
	1d935a1 Browse files » docs: marvell: update mv_ddr branch ... Now that the BLE image sources (mv_ddr) are updated, reflect the proper branch in the Armada build howto. Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 4 Oct 2020
	fc8dc49 Browse files » plat: marvell: armada: a3k: rename the UART images archive ... Add *.bin extension to UART recovery images archive name. Such naming will cause the UART recovery images to be copied to the Buildroot output folder upon flash image build. Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 24 Oct 2019 Marcin Wojtas committed on 4 Oct 2020
	270367f Browse files » plat: marvell: armada: a3k: allow image load to RAM address 0 ... Marvell uses RAM address 0x0 for loading BL33 stage images. When ATF is built with DEBUG=1, its IO subsystem fails on assert checking the destination RAM address != 0. This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform allowing to bypass the above check in debug mode. Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 27 Aug 2019 Marcin Wojtas committed on 4 Oct 2020
	ff9cfdc Browse files » marvell: comphy: cp110: add support for USB comphy polarity invert ... The polarity inversion for USB was not tested due to lack of hw design which requires it. Currently all supported boards doesn't require USB phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Enable the option for the ones that need it. Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	38f6dac Browse files » marvell: comphy: cp110: add support for SATA comphy polarity invert ... The cp110 comphy has ability to invert RX and/or TX polarity. Polarity depends on board design. Currently all supported boards doesn't require SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	8fa1340 Browse files » marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353 ... According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should be toggled in addition to the XFI/SFI PHY reset. Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 4 Oct 2020
	11e6ed0 Browse files » drivers: marvell: mochi: Update AP incoming masters secure level ... Do not force non-secure access level for PIDI masters when LLC_SRAM is enabled. The EIP197 is located on CP0 and need to access secure SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not changed when forwarded to address decoding tables. Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 22 Aug 2019 Marcin Wojtas committed on 4 Oct 2020
	a9688f0 Browse files » plat: marvell: armada: add ccu window for workaround errata-id 3033912 ... Added ccu window to allow access to addresses in the range [0xf100_0000, 0xf1ff_ffff]. Change-Id: I63ee68338d674114d01cd627198dc907653493e8 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 25 Dec 2019 Marcin Wojtas committed on 4 Oct 2020
	6792ba1 Browse files » plat: marvell: ap806: implement workaround for errata-id FE-4265711 ... ERRATA ID: FE-4265711 - Incorrect CNTVAL reading CNTVAL reflects the global system counter value in binary format. Due to this erratum, the CNTVAL value presented to the processor may be incorrect for several clock cycles. Workaround: Override the default value of AP Register Device General control 20 [19:16] and AP Register Device General Control 21 [11:8] to the value of 0x3. Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Stefan Chulski authored on 24 Jun 2019 Marcin Wojtas committed on 4 Oct 2020
2020-10-03	2539dd3 Browse files » Merge "libfdt: Upgrade libfdt source files" into integration Alexei Fedorov authored on 3 Oct 2020 TrustedFirmware Code Review committed on 3 Oct 2020
	c2c03e7 Browse files » Merge "spmd: Fix signedness comparison warning" into integration Alexei Fedorov authored on 3 Oct 2020 TrustedFirmware Code Review committed on 3 Oct 2020
	55ff05f Browse files » Workaround for Cortex A76 erratum 1868343 ... Cortex A76 erratum 1868343 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call. SDEN can be found here: https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d johpow01 authored on 29 Sep 2020 Alexei Fedorov committed on 3 Oct 2020
2020-10-02	950e37d Browse files » Merge "morello: Add Morello platform documentation" into integration Madhukar Pappireddy authored on 2 Oct 2020 TrustedFirmware Code Review committed on 2 Oct 2020
	dc57bea Browse files » Merge "fdts: stm32mp1: realign device tree with kernel" into integration Madhukar Pappireddy authored on 2 Oct 2020 TrustedFirmware Code Review committed on 2 Oct 2020
	3b45666 Browse files » libfdt: Upgrade libfdt source files ... Update the libfdt source files, the upstream commit is 73e0f143b73d ("libfdt: fdt_strerror(): Fix comparison warning"). This brings us the fixes for the signed/unsigned comparison warnings, so platforms can enable -Wsign-compare now. Change-Id: I303d891c82ffea0acefdde27289339db5ac5a289 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara authored on 1 Oct 2020 Alexei Fedorov committed on 2 Oct 2020
	6e4da01 Browse files » spmd: Fix signedness comparison warning ... With -Wsign-compare, compilers issue a warning in the SPMD code: ==================== services/std_svc/spmd/spmd_pm.c:35:22: error: comparison of integer expressions of different signedness: 'int' and 'unsigned int' [-Werror=sign-compare] 35 \| if ((id < 0) \|\| (id >= PLATFORM_CORE_COUNT)) { \| ^~ cc1: all warnings being treated as errors ==================== Since we just established that "id" is positive, we can safely cast it to an unsigned type to make the comparison have matching types. Change-Id: I6ef24804c88136d7e3f15de008e4fea854f10ffe Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara authored on 2 Oct 2020 Alexei Fedorov committed on 2 Oct 2020
	14bac44 Browse files » Merge "morello: Add changes to fix build of Morello Platform" into integration Alexei Fedorov authored on 2 Oct 2020 TrustedFirmware Code Review committed on 2 Oct 2020
	8445253 Browse files » morello: Add Morello platform documentation ... Morello platform has a SCP which brings the primary Rainier CPU out of reset which starts executing at BL31. This patch provides documentation support for Morello platform. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2 Chandni Cherukuri authored on 1 Oct 2020 chandni cherukuri committed on 2 Oct 2020