Remove all checkpatch errors from codebase ...

Exclude stdlib files because they do not follow kernel code style.

Fixes ARM-software/tf-issues#73

Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab

Merge pull request #145 from athoelke/at/psci-memory-optimization-v2 ...

PSCI memory optimizations (v2)

Merge pull request #144 from athoelke/at/init-context-v2 ...

Initialise CPU contexts from entry_point_info (v2)

Correctly dimension the PSCI aff_map_node array ...

The array of affinity nodes is currently allocated for 32 entries
with the PSCI_NUM_AFFS value defined in psci.h. This is not enough
for large systems, and will substantially over allocate the array
for small systems.

This patch introduces an optional platform definition
PLATFORM_NUM_AFFS to platform_def.h. If defined this value is
used for PSCI_NUM_AFFS, otherwise a value of two times the number
of CPU cores is used.

The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves
nearly 1.5KB of memory.

Fixes ARM-software/tf-issues#192

Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445

Eliminate psci_suspend_context array ...

psci_suspend_context is an array of cache-line aligned structures
containing the single power_state integer per cpu. This array is
the only structure indexed by the aff_map_node.data integer.

This patch saves 2KB of BL3-1 memory by placing the CPU
power_state value directly in the aff_map_node structure. As a
result, this value is now never cached and the cache clean when
writing the value is no longer required.

Fixes ARM-software/tf-issues#195

Change-Id: Ib4c70c8f79eed295ea541e7827977a588a19ef9b

Initialise CPU contexts from entry_point_info ...

Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
*  The first uses entry_point_info to initialize the relevant
   cpu_context for first entry into a lower exception level on a CPU
*  The second populates the EL1 and EL2 system registers as needed
   from the cpu_context to ensure correct entry into the lower EL

This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).

In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.

Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f

Merge pull request #143 from athoelke/at/remove-nsram ...

Remove NSRAM from FVP memory map

Merge pull request #140 from athoelke/at/psci_smc_handler ...

PSCI SMC handler improvements

Merge pull request #138 from athoelke/at/cpu-context ...

Move CPU context pointers into cpu_data

Merge pull request #137 from athoelke/at/no-early-exceptions ...

Remove early_exceptions from BL3-1

Merge pull request #136 from athoelke/at/cpu-data ...

Per-cpu data cache restructuring

Merge pull request #142 from athoelke/at/fix-console_putc ...

Remove broken assertion in console_putc()

Remove NSRAM from FVP memory map ...

This memory is not used by the FVP port and requires an additional
4KB translation table.

This patch removes the entry from the memory map and reduces the
number of allocated translation tables.

Fixes ARM-software/tf-issues#196

Change-Id: I5b959e4fe92f5f892ed127c40dbe6c85eed3ed72

Remove broken assertion in console_putc() ...

The assertion in console_putc() would trigger a recursion that
exhausts the stack and eventually aborts.

This patch replaces the assertion with an error return if the
console has not been initialized yet.

Fixes ARM-software/tf-issues#208

Change-Id: I95f736ff215d69655eb5ba7ceac70dc1409d986a

Merge pull request #135 from soby-mathew/sm/remove-reinit-of-timers ...

Remove re-initialisation of system timers after warm boot for FVP

Remove re-initialisation of system timers after warm boot for FVP ...

This patch removes the reinitialisation of memory mapped system timer
registers after a warm boot for the FVP. The system timers in FVP are
in the 'Always ON' power domain which meant the reinitialisation was
redundant and it could have conflicted with the setup the normal
world has done.

The programming of CNTACR(x) and CNTNSAR, the system timer registers,
are removed from the warm boot path with this patch.

Fixes ARM-software/tf-issues#169

Change-Id: Ie982eb03d1836b15ef3cf1568de2ea68a08b443e

Merge pull request #134 from jcastillo-arm/jc/tf-issues/179 ...

Set correct value for SYS_ID_REV_SHIFT in FVP

Remove early_exceptions from BL3-1 ...

The crash reporting support and early initialisation of the
cpu_data allow the runtime_exception vectors to be used from
the start in BL3-1, removing the need for the additional
early_exception vectors and 2KB of code from BL3-1.

Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871

Move CPU context pointers into cpu_data ...

Moving the context pointers for each CPU into the per-cpu data
allows for much more efficient access to the contexts for the
current CPU.

Change-Id: Id784e210d63cbdcddb44ac1591617ce668dbc29f

Per-cpu data cache restructuring ...

This patch prepares the per-cpu pointer cache for wider use by:
* renaming the structure to cpu_data and placing in new header
* providing accessors for this CPU, or other CPUs
* splitting the initialization of the TPIDR pointer from the
  initialization of the cpu_data content
* moving the crash stack initialization to a crash stack function
* setting the TPIDR pointer very early during boot

Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3

Set correct value for SYS_ID_REV_SHIFT in FVP ...

According to documentation, the Rev field is located at bit 28 in
the V2M sysid register.

Fixes ARM-software/tf-issues#179

Change-Id: I2abb7bdc092ccd3f41f8962dc8d8d8e44e8dfdc3

Merge pull request #133 from athoelke/at/crash-reporting-opt ...

Make the BL3-1 crash reporting optional

Merge pull request #131 from athoelke/at/cm_get_context ...

Provide cm_get/set_context() for current CPU

Merge pull request #130 from athoelke/at/inline-asm-sysreg-v2 ...

Make system register functions inline assembly v2

Merge pull request #128 from sandrine-bailleux/sb/make-load_image-ep-optional ...

Make the entry point argument optional in load_image()

Merge pull request #127 from sandrine-bailleux/sb/fix-pl011-fifo-polling ...

PL011: Fix a bug in the UART FIFO polling

Merge pull request #126 from sandrine-bailleux/sb/include-missing-hfile ...

Include 'platform_def.h' header file in 'crash_reporting.S'

Merge pull request #125 from sandrine-bailleux/sb/remove-bl2_el_change_mem_ptr ...

fvp: Remove unused 'bl2_el_change_mem_ptr' variable

Make the BL3-1 crash reporting optional ...

This patch makes the console crash dump of processor register
state optional based on the CRASH_REPORTING make variable.

This defaults to only being enabled for DEBUG builds. This can
be overridden by setting a different value in the platform
makefile or on the make command line.

Change-Id: Icfa1b2d7ff0145cf0a85e8ad732f9cee7e7e993f

Provide cm_get/set_context() for current CPU ...

All callers of cm_get_context() pass the calling CPU MPIDR to the
function. Providing a specialised version for the current
CPU results in a reduction in code size and better readability.

The current function has been renamed to cm_get_context_by_mpidr()
and the existing name is now used for the current-CPU version.

The same treatment has been done to cm_set_context(), although
only both forms are used at present in the PSCI and TSPD code.

Change-Id: I91cb0c2f7bfcb950a045dbd9ff7595751c0c0ffb