2014-05-22 |
Merge pull request #85 from hliebel/hl/bl30-doc
...
Improve BL3-0 documentation
Andrew Thoelke
committed
on 22 May 2014
|
2014-05-20 |
Address issue 156: 64-bit addresses get truncated
...
Addresses were declared as "unsigned int" in drivers/arm/peripherals/pl011/pl011.h and in function init_xlation_table. Changed to use "unsigned long" instead
Fixes ARM-software/tf-issues#156
Lin Ma
committed
on 20 May 2014
|
2014-05-19 |
Improve BL3-0 documentation
...
Provide some information about the expected use of BL3-0.
Fixes ARM-software/tf-issues#144
Change-Id: I5c8d59a675578394be89481ae4ec39ca37522750
Harry Liebel
committed
on 19 May 2014
|
Merge pull request #78 from jeenuv:tf-issues-148
Andrew Thoelke
committed
on 19 May 2014
|
2014-05-16 |
Add build configuration for timer save/restore
...
At present, non-secure timer register contents are saved and restored as
part of world switch by BL3-1. This effectively means that the
non-secure timer stops, and non-secure timer interrupts are prevented
from asserting until BL3-1 switches back, introducing latency for
non-secure services. Often, secure world might depend on alternate
sources for secure interrupts (secure timer or platform timer) instead
of non-secure timers, in which case this save and restore is
unnecessary.
This patch introduces a boolean build-time configuration NS_TIMER_SWITCH
to choose whether or not to save and restore non-secure timer registers
upon world switch. The default choice is made not to save and restore
them.
Fixes ARM-software/tf-issues#148
Change-Id: I1b9d623606acb9797c3e0b02fb5ec7c0a414f37e
Jeenu Viswambharan
committed
on 16 May 2014
|
Document summary of build options in user guide
...
Change-Id: I6bd077955bf3780168a874705974bbe72ea0f5f1
Jeenu Viswambharan
committed
on 16 May 2014
|
Reorganize build options
...
At present, various build options are initialized at various places in
the Makefile. This patch gathers all build option declarations at the
top of the Makefile and assigns them default values.
Change-Id: I9f527bc8843bf69c00cb754dc60377bdb407a951
Jeenu Viswambharan
committed
on 16 May 2014
|
Introduce convenience functions to build
...
This patch introduces two convenience functions to the build system:
- assert_boolean: asserts that a given option is assigned either 0 or
1 as values
- add_define: helps add/append macro definitions to build tool command
line. This also introduces the variable DEFINES which is used to
collect and pass all relevant configurations to build tools
Change-Id: I3126894b034470d39858ebb3bd183bda681c7126
Jeenu Viswambharan
committed
on 16 May 2014
|
Set SCR_EL3.RW correctly before exiting bl31_main
...
SCR_EL3.RW was not updated immediately before exiting bl31_main() and
running BL3-3. If a AArch32 Secure-EL1 Payload had just been
initialised, then the SCR_EL3.RW bit would be left indicating a
32-bit BL3-3, which may not be correct.
This patch explicitly sets SCR_EL3.RW appropriately based on the
provided SPSR_EL3 value for the BL3-3 image.
Fixes ARM-software/tf-issues#126
Change-Id: Ic7716fe8bc87e577c4bfaeb46702e88deedd9895
Andrew Thoelke
committed
on 16 May 2014
|
Rework BL3-1 unhandled exception handling and reporting
...
This patch implements the register reporting when unhandled exceptions are
taken in BL3-1. Unhandled exceptions will result in a dump of registers
to the console, before halting execution by that CPU. The Crash Stack,
previously called the Exception Stack, is used for this activity.
This stack is used to preserve the CPU context and runtime stack
contents for debugging and analysis.
This also introduces the per_cpu_ptr_cache, referenced by tpidr_el3,
to provide easy access to some of BL3-1 per-cpu data structures.
Initially, this is used to provide a pointer to the Crash stack.
panic() now prints the the error file and line number in Debug mode
and prints the PC value in release mode.
The Exception Stack is renamed to Crash Stack with this patch.
The original intention of exception stack is no longer valid
since we intend to support several valid exceptions like IRQ
and FIQ in the trusted firmware context. This stack is now
utilized for dumping and reporting the system state when a
crash happens and hence the rename.
Fixes ARM-software/tf-issues#79 Improve reporting of unhandled exception
Change-Id: I260791dc05536b78547412d147193cdccae7811a
Soby Mathew
committed
on 16 May 2014
|
Merge pull request #71 from sandrine-bailleux:sb/fix-tsp-fvp-makefile
Andrew Thoelke
committed
on 16 May 2014
|
Merge pull request #69 from sandrine-bailleux:sb/split-mmu-fcts-per-el
Andrew Thoelke
committed
on 16 May 2014
|
Merge pull request #68 from jcastillo-arm/jc/tf-issues/137
...
Change-Id: If8744c38c2d5c50caa7454b055e2ba418cf1e8bf
Andrew Thoelke
committed
on 16 May 2014
|
Merge pull request #66 from athoelke/tzc-config-fix
...
Fixes for TZC configuration on FVP
danh-arm
committed
on 16 May 2014
|
2014-05-13 |
fvp: Use the right implem. of plat_report_exception() in BL3-2
...
On FVP, the file 'plat/fvp/aarch64/plat_helpers.S' contains an
FVP-specific implementation of the function 'plat_report_exception()',
which is meant to override the default implementation. However, this
file was not included into the BL3-2 image, meaning it was still
using the default implementation. This patch fixes the FVP makefile
to compile this file in.
Change-Id: I3d44b9ec3a9de7e2762e0887d3599b185d3e28d2
Sandrine Bailleux
committed
on 13 May 2014
|
Fix C accessors to GIC distributor registers with set/clear semantics
...
This patch fixes C accessors to GIC registers that follow a set/clear
semantic to change the state of an interrupt, instead of read/write/modify.
These registers are:
Set-Enable
Clear-Enable
Set-Pending
Clear-Pending
Set-Active
Clear-Active
For instance, to enable an interrupt we write a one to the corresponding bit
in the Set-Enable register, whereas to disable it we write a one to the
corresponding bit in the Clear-Enable register.
Fixes ARM-software/tf-issues#137
Change-Id: I3b66bad94d0b28e0fe08c9042bac0bf5ffa07944
Juan Castillo
committed
on 13 May 2014
|
2014-05-12 |
Fix broken standby state implementation in PSCI
...
This patch fixes the broken support for entry into standby states
introduced under commit-id 'd118f9f864' (tf-issues#94). Upon exit from
the platform defined standby state instead of returning to the caller
of the SMC, execution would get stuck in the wfi instruction meant for
entering a power down state. This patch ensures that exit from a
standby state and entry into a power down state do not interfere with
each other.
Fixes ARM-software/tf-issues#154
Change-Id: I56e5df353368e44d6eefc94ffedefe21929f5cfe
Achin Gupta
committed
on 12 May 2014
|
Fixes for TZC configuration on FVP
...
The TZC configuration on FVP was incorrectly allowing both secure
and non-secure accesses to the DRAM, which can cause aliasing
problems for software. It was also not enabling virtio access on
some models.
This patch fixes both of those issues. The patch also enabless
non-secure access to the DDR RAM for all devices with defined IDs.
The third region of DDR RAM has been removed from the configuration
as this is not used in any of the FVP models.
Fixes ARM-software/tf-issues#150
Fixes ARM-software/tf-issues#151
Change-Id: I60ad5daaf55e14f178affb8afd95d17e7537abd7
Andrew Thoelke
committed
on 12 May 2014
|
2014-05-09 |
fvp: Provide per-EL MMU setup functions
...
Instead of having a single version of the MMU setup functions for all
bootloader images that can execute either in EL3 or in EL1, provide
separate functions for EL1 and EL3. Each bootloader image can then
call the appropriate version of these functions. The aim is to reduce
the amount of code compiled in each BL image by embedding only what's
needed (e.g. BL1 to embed only EL3 variants).
Change-Id: Ib86831d5450cf778ae78c9c1f7553fe91274c2fa
Sandrine Bailleux
committed
on 9 May 2014
|
Introduce IS_IN_ELX() macros
...
The goal of these macros is to improve code readability by providing
a concise way to check whether we are running in the expected
exception level.
Change-Id: If9aebadfb6299a5196e9a582b442f0971d9909b1
Sandrine Bailleux
committed
on 9 May 2014
|
2014-05-08 |
Merge pull request #65 from vikramkanigiri/vk/console_init
...
Ensure a console is initialized before it is used
danh-arm
committed
on 8 May 2014
|
Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1
...
Preserve x19-x29 across world switch for exception handling
danh-arm
committed
on 8 May 2014
|
Ensure a console is initialized before it is used
...
This patch moves console_init() to bl32_early_platform_setup(). It
also ensures that console_init() is called in each
blX_early_platform_setup() function before the console is used
e.g. through a printf call in an assert() statement.
Fixes ARM-software/TF-issues#127
Change-Id: I5b1f17e0152bab674d807d2a95ff3689c5d4794e
Vikram Kanigiri
committed
on 8 May 2014
|
Merge pull request #62 from athoelke/set-little-endian-v2
...
Set processor endianness immediately after RESET v2
danh-arm
committed
on 8 May 2014
|
Preserve x19-x29 across world switch for exception handling
...
Previously exception handlers in BL3-1, X19-X29 were not saved
and restored on every SMC/trap into EL3. Instead these registers
were 'saved as needed' as a side effect of the A64 ABI used by the C
compiler.
That approach failed when world switching but was not visible
with the TSP/TSPD code because the TSP is 64-bit, did not
clobber these registers when running and did not support pre-emption
by normal world interrupts. These scenarios showed
that the values in these registers can be passed through a world
switch, which broke the normal and trusted world assumptions
about these registers being preserved.
The Ideal solution saves and restores these registers when a
world switch occurs - but that type of implementation is more complex.
So this patch always saves and restores these registers on entry and
exit of EL3.
Fixes ARM-software/tf-issues#141
Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
Soby Mathew
committed
on 8 May 2014
|
Merge pull request #58 from athoelke/optimise-cache-flush-v2
...
Optimise data cache clean/invalidate operation v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #61 from athoelke/use-mrs-msr-from-assembler-v2
...
Use MRS/MSR instructions in assembler code v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #60 from athoelke/disable-mmu-v2
...
Replace disable_mmu with assembler version v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #59 from athoelke/review-barriers-v2
...
Correct usage of data and instruction barriers v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #57 from sandrine-bailleux/sb/remove-pl011-base
...
Remove unused 'PL011_BASE' macro
danh-arm
committed
on 8 May 2014
|