2014-07-10 |
Merge pull request #157 from sandrine-bailleux/sb/tf-issue-109
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TF issue 109
danh-arm
committed
on 10 Jul 2014
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Merge pull request #146 from danh-arm/dh/refactor-fvp-gic
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Refactor fvp config and gic code
danh-arm
committed
on 10 Jul 2014
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Merge pull request #161 from danh-arm/lm/calc-tcr-bits
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Calculate TCR bits based on VA and PA
danh-arm
committed
on 10 Jul 2014
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2014-07-09 |
Refactor fvp gic code to be a generic driver
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Refactor the FVP gic code in plat/fvp/fvp_gic.c to be a generic ARM
GIC driver in drivers/arm/gic/arm_gic.c. Provide the platform
specific inputs in the arm_gic_setup() function so that the driver
has no explicit dependency on platform code.
Provide weak implementations of the platform interrupt controller
API in a new file, plat/common/plat_gic.c. These simply call through
to the ARM GIC driver.
Move the only remaining FVP GIC function, fvp_gic_init() to
plat/fvp/aarch64/fvp_common.c and remove plat/fvp/fvp_gic.c
Fixes ARM-software/tf-issues#182
Change-Id: Iea82fe095fad62dd33ba9efbddd48c57717edd21
Dan Handley
committed
on 9 Jul 2014
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Refactor fvp_config into common platform header
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Changed the fvp_config array in fvp_common.c into a struct and
moved into a new optional common platform header,
include/plat/common/plat_config.h. Removed the config definitions
in fvp_def.h and updated all references to the platform config.
This makes the interface to the platform config cleaner and uses
a little less RAM.
Fixes ARM-software/tf-issues#180
Change-Id: I58dd7b3c150f24f7ee230a26fd57c827853ba803
Dan Handley
committed
on 9 Jul 2014
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Calculate TCR bits based on VA and PA
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Currently the TCR bits are hardcoded in xlat_tables.c. In order to
map higher physical address into low virtual address, the TCR bits
need to be configured accordingly.
This patch is to save the max VA and PA and calculate the TCR.PS/IPS
and t0sz bits in init_xlat_tables function.
Change-Id: Ia7a58e5372b20200153057d457f4be5ddbb7dae4
Lin Ma
authored
on 27 Jun 2014
Dan Handley
committed
on 9 Jul 2014
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2014-07-01 |
fvp: Properly detect the location of BL1 R/W data
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There was already a rudimentary mechanism to detect whether BL1
R/W data was loaded at the top or bottom of memory. Basically,
- either BL1 was loaded at the very end of the trusted RAM
- in all other cases BL1 was considered sitting at the bottom of
the memory and the memory usage structure was updated accordingly,
potentially resulting in critical memory waste.
For instance, if BL1 R/W base address was set to
(TZRAM_END - 4096 - bl1_size), it would virtually occupy the whole
memory.
This patch improves the mechanism to detect the location of BL1
to avoid such scenarios.
Change-Id: I224a9edf0fe8d34208545d84b28b63f2bb830d03
Sandrine Bailleux
committed
on 1 Jul 2014
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Remove concept of top/bottom image loading
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This concept is no longer required since we now support loading of
images at fixed addresses only.
The image loader now automatically detects the position of the image
inside the current memory layout and updates the layout such that
memory fragmentation is minimised.
The 'attr' field of the meminfo data structure, which used to hold
the bottom/top loading information, has been removed. Also the 'next'
field has been removed as it wasn't used anywhere.
The 'init_bl2_mem_layout()' function has been moved out of common
code and put in BL1-specific code. It has also been renamed into
'bl1_init_bl2_mem_layout'.
Fixes ARM-software/tf-issues#109
Change-Id: I3f54642ce7b763d5ee3b047ad0ab59eabbcf916d
Sandrine Bailleux
committed
on 1 Jul 2014
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2014-06-27 |
Merge pull request #151 from vikramkanigiri/vk/t133-code-readability
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Simplify entry point information generation code on FVP
Andrew Thoelke
committed
on 27 Jun 2014
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Merge pull request #155 from athoelke/at/support-foundation-v2.1
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Support later revisions of the Foundation FVP
Andrew Thoelke
committed
on 27 Jun 2014
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Support later revisions of the Foundation FVP
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The code in the FVP port which checks the platform type and
revision information in the SYS_ID register strictly supported
only the first revision of the Base and Foundation FVPs.
The current check also does not reflect the fact that the
board revision field is 'local' to the board type (HBI field).
Support for a new Foundation model is required now, and the
checking code is relaxed to allow execution (with a diagnostic)
on unrecognised revisions of the Base and Foundation FVP.
Change-Id: I7cd3519dfb56954aafe5f52ce1fcea0ee257ba9f
Andrew Thoelke
committed
on 27 Jun 2014
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2014-06-26 |
Merge pull request #154 from athoelke/at/inline-mmio
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Inline the mmio accessor functions
Andrew Thoelke
committed
on 26 Jun 2014
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Merge pull request #153 from athoelke/at/remove-psci-mpidr
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Remove current CPU mpidr from PSCI common code
Andrew Thoelke
committed
on 26 Jun 2014
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2014-06-25 |
Remove current CPU mpidr from PSCI common code
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Many of the interfaces internal to PSCI pass the current CPU
MPIDR_EL1 value from function to function. This is not required,
and with inline access to the system registers is less efficient
than requiring the code to read that register whenever required.
This patch remove the mpidr parameter from the affected interfaces
and reduces code in FVP BL3-1 size by 160 bytes.
Change-Id: I16120a7c6944de37232016d7e109976540775602
Andrew Thoelke
committed
on 25 Jun 2014
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2014-06-24 |
Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2
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Remove all checkpatch errors from codebase
danh-arm
committed
on 24 Jun 2014
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Merge pull request #150 from sandrine-bailleux/sb/fix-plat-print-gic-regs
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fvp: Fix register name in 'plat_print_gic_regs' macro
danh-arm
committed
on 24 Jun 2014
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Merge pull request #149 from sandrine-bailleux/sb/warn-missing-include-dirs
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Compile with '-Wmissing-include-dirs' flag
danh-arm
committed
on 24 Jun 2014
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Merge pull request #147 from athoelke/at/remove-bakery-mpidr
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Remove calling CPU mpidr from bakery lock API
danh-arm
committed
on 24 Jun 2014
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Inline the mmio accessor functions
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Making the simple mmio_read_*() and mmio_write_*() functions inline
saves 360 bytes of code in FVP release build.
Fixes ARM-software/tf-issues#210
Change-Id: I65134f9069f3b2d8821d882daaa5fdfe16355e2f
Andrew Thoelke
committed
on 24 Jun 2014
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Remove all checkpatch errors from codebase
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Exclude stdlib files because they do not follow kernel code style.
Fixes ARM-software/tf-issues#73
Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
Juan Castillo
committed
on 24 Jun 2014
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Simplify entry point information generation code on FVP
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This patch reworks FVP specific code responsible for determining
the entry point information for BL3-2 and BL3-3 stages when BL3-1
is configured as the reset handler.
Change-Id: Ia661ff0a6a44c7aabb0b6c1684b2e8d3642d11ec
Vikram Kanigiri
committed
on 24 Jun 2014
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fvp: Fix register name in 'plat_print_gic_regs' macro
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The 'plat_print_gic_regs' macro was accessing the GICC_CTLR register
using the GICD_CTLR offset. This still generates the right code in
the end because GICD_CTLR == GICC_CTLR but this patch fixes it for
the logic of the code.
Change-Id: I7b17af50e587f07bec0e4c933e346088470c96f3
Sandrine Bailleux
committed
on 24 Jun 2014
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2014-06-23 |
Remove calling CPU mpidr from bakery lock API
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The bakery lock code currently expects the calling code to pass
the MPIDR_EL1 of the current CPU.
This is not always done correctly. Also the change to provide
inline access to system registers makes it more efficient for the
bakery lock code to obtain the MPIDR_EL1 directly.
This change removes the mpidr parameter from the bakery lock
interface, and results in a code reduction of 160 bytes for the
ARM FVP port.
Fixes ARM-software/tf-issues#213
Change-Id: I7ec7bd117bcc9794a0d948990fcf3336a367d543
Andrew Thoelke
committed
on 23 Jun 2014
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Merge pull request #145 from athoelke/at/psci-memory-optimization-v2
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PSCI memory optimizations (v2)
danh-arm
committed
on 23 Jun 2014
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Merge pull request #144 from athoelke/at/init-context-v2
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Initialise CPU contexts from entry_point_info (v2)
danh-arm
committed
on 23 Jun 2014
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Correctly dimension the PSCI aff_map_node array
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The array of affinity nodes is currently allocated for 32 entries
with the PSCI_NUM_AFFS value defined in psci.h. This is not enough
for large systems, and will substantially over allocate the array
for small systems.
This patch introduces an optional platform definition
PLATFORM_NUM_AFFS to platform_def.h. If defined this value is
used for PSCI_NUM_AFFS, otherwise a value of two times the number
of CPU cores is used.
The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves
nearly 1.5KB of memory.
Fixes ARM-software/tf-issues#192
Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
Andrew Thoelke
committed
on 23 Jun 2014
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Eliminate psci_suspend_context array
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psci_suspend_context is an array of cache-line aligned structures
containing the single power_state integer per cpu. This array is
the only structure indexed by the aff_map_node.data integer.
This patch saves 2KB of BL3-1 memory by placing the CPU
power_state value directly in the aff_map_node structure. As a
result, this value is now never cached and the cache clean when
writing the value is no longer required.
Fixes ARM-software/tf-issues#195
Change-Id: Ib4c70c8f79eed295ea541e7827977a588a19ef9b
Andrew Thoelke
committed
on 23 Jun 2014
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Initialise CPU contexts from entry_point_info
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Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
Andrew Thoelke
committed
on 23 Jun 2014
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Merge pull request #143 from athoelke/at/remove-nsram
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Remove NSRAM from FVP memory map
danh-arm
committed
on 23 Jun 2014
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Merge pull request #140 from athoelke/at/psci_smc_handler
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PSCI SMC handler improvements
danh-arm
committed
on 23 Jun 2014
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