2014-08-12 |
Merge pull request #183 from danh-arm/dh/print_output2
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Add concept of console output log levels
Rationalize console log output
danh-arm
committed
on 12 Aug 2014
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Rationalize console log output
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Fix the following issues with the console log output:
* Make sure the welcome string is the first thing in the log output
(during normal boot).
* Prefix each message with the BL image name so it's clear which
BL the output is coming from.
* Ensure all output is wrapped in one of the log output macros so it can
be easily compiled out if necessary. Change some of the INFO() messages
to VERBOSE(), especially in the TSP.
* Create some extra NOTICE() and INFO() messages during cold boot.
* Remove all usage of \r in log output.
Fixes ARM-software/tf-issues#231
Change-Id: Ib24f7acb36ce64bbba549f204b9cde2dbb46c8a3
Dan Handley
committed
on 12 Aug 2014
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Add concept of console output log levels
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Create new LOG_LEVEL build option, which controls the amount of
console output compiled into the build. This should be one of the
following:
0 (LOG_LEVEL_NONE)
10 (LOG_LEVEL_NOTICE)
20 (LOG_LEVEL_ERROR)
30 (LOG_LEVEL_WARNING)
40 (LOG_LEVEL_INFO)
50 (LOG_LEVEL_VERBOSE)
All log output up to and including the log level is compiled into the
build. The default value is 40 in debug builds and 20 in release
builds.
Complement the existing INFO, WARN and ERROR console output macros
with NOTICE and VERBOSE macros, which are conditionally compiled in
depending on the value of LOG_LEVEL.
Fixes ARM-software/tf-issues#232
Change-Id: I951e2f333e7b90fc4b1060741d9a6db699d5aa72
Dan Handley
committed
on 12 Aug 2014
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Merge pull request #182 from soby-mathew/sm/stack_optimize
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Reduce runtime stack size and add compilation macro for each BL stage
danh-arm
committed
on 12 Aug 2014
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Merge pull request #180 from jcastillo-arm/jc/tf-issues/207
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Move up to Linaro 14.07 toolchain
danh-arm
committed
on 12 Aug 2014
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2014-08-11 |
Reduce the runtime stack size in BL stages.
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This patch separates the stack size for each BL stage and
reduces it after stack usage analysis was done.
Fixes ARM-software/tf-issues#200
Change-Id: I8edc6de2551b0a6788761d121937692b2149bb29
Soby Mathew
committed
on 11 Aug 2014
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Add compilation macro for each BL stage
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This patch defines a compile time macro for each boot loader stage
which allows compilation of code only for a specific stage.
Change-Id: I3a4068404cd3dc26d652556ca9ca7afea8dd28ef
Soby Mathew
committed
on 11 Aug 2014
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2014-08-07 |
Move up to Linaro 14.07 toolchain
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Tests show a slight reduction in code size compared to 13.11.
User guide updated.
Fixes ARM-software/tf-issues#207
Change-Id: I9b80a5d7820cdfd443cac4d4b63f925b74a8c3a3
Juan Castillo
committed
on 7 Aug 2014
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2014-08-04 |
Merge pull request #179 from jcastillo-arm/jc/tf-issues/219
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Call platform_is_primary_cpu() only from reset handler
danh-arm
committed
on 4 Aug 2014
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Merge pull request #178 from soby-mathew/sm/optmize_el3_context
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Optimize EL3 register state stored in cpu_context structure
danh-arm
committed
on 4 Aug 2014
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2014-08-01 |
Merge pull request #175 from vikramkanigiri/vk/spd-init-by-stack-unwinding
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Vk/spd init by stack unwinding
danh-arm
committed
on 1 Aug 2014
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Support asynchronous method for BL3-2 initialization
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This patch adds support for BL3-2 initialization by asynchronous
method where BL3-1 transfers control to BL3-2 using world switch.
After BL3-2 initialization, it transfers control to BL3-3 via SPD
service handler. The SPD service handler initializes the CPU context
to BL3-3 entrypoint depending on the return function indentifier from
TSP initialization.
Fixes ARM-software/TF-issues#184
Change-Id: I7b135c2ceeb356d3bb5b6a287932e96ac67c7a34
Vikram Kanigiri
committed
on 1 Aug 2014
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Rework the TSPD setup code
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There is no mechanism which allows the TSPD to specify what SPSR to
use when entering BL3-2 instead of BL3-3. This patch divides the
responsibility between tspd_setup() and tspd_init() for initializing
the TSPD and TSP to support the alternate BL3-2 initialization flow
where BL3-1 handsover control to BL3-2 instead of BL3-3.
SPSR generated by TSPD for TSP is preserved due the new division of
labour which fixes #174.
This patch also moves the cpu_context initialization code from
tspd_setup() to tspd_init() immediately before entering the TSP.
Instead tspd_setup() updates the BL3-2 entrypoint info structure
with the state required for initializing the TSP later.
Fixes ARM-software/TF-issues#174
Change-Id: Ida0a8a48d466c71d5b07b8c7f2af169b73f96940
Vikram Kanigiri
committed
on 1 Aug 2014
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Call platform_is_primary_cpu() only from reset handler
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The purpose of platform_is_primary_cpu() is to determine after reset
(BL1 or BL3-1 with reset handler) if the current CPU must follow the
cold boot path (primary CPU), or wait in a safe state (secondary CPU)
until the primary CPU has finished the system initialization.
This patch removes redundant calls to platform_is_primary_cpu() in
subsequent bootloader entrypoints since the reset handler already
guarantees that code is executed exclusively on the primary CPU.
Additionally, this patch removes the weak definition of
platform_is_primary_cpu(), so the implementation of this function
becomes mandatory. Removing the weak symbol avoids other
bootloaders accidentally picking up an invalid definition in case the
porting layer makes the real function available only to BL1.
The define PRIMARY_CPU is no longer mandatory in the platform porting
because platform_is_primary_cpu() hides the implementation details
(for instance, there may be platforms that report the primary CPU in
a system register). The primary CPU definition in FVP has been moved
to fvp_def.h.
The porting guide has been updated accordingly.
Fixes ARM-software/tf-issues#219
Change-Id: If675a1de8e8d25122b7fef147cb238d939f90b5e
Juan Castillo
committed
on 1 Aug 2014
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2014-07-31 |
Optimize EL3 register state stored in cpu_context structure
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This patch further optimizes the EL3 register state stored in
cpu_context. The 2 registers which are removed from cpu_context are:
* cntfrq_el0 is the system timer register which is writable
only in EL3 and it can be programmed during cold/warm boot. Hence
it need not be saved to cpu_context.
* cptr_el3 controls access to Trace, Floating-point, and Advanced
SIMD functionality and it is programmed every time during cold
and warm boot. The current BL3-1 implementation does not need to
modify the access controls during normal execution and hence
they are expected to remain static.
Fixes ARM-software/tf-issues#197
Change-Id: I599ceee3b73a7dcfd37069fd41b60e3d397a7b18
Soby Mathew
committed
on 31 Jul 2014
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2014-07-28 |
Merge pull request #177 from jcastillo-arm/jc/tf-issues/096
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Rework incorrect use of assert() and panic() in codebase
danh-arm
committed
on 28 Jul 2014
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Merge pull request #172 from soby-mathew/sm/asm_assert
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Introduce asm assert and optimize crash reporting
danh-arm
committed
on 28 Jul 2014
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Merge pull request #170 from achingupta/ag/tf-issues#226
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Simplify management of SCTLR_EL3 and SCTLR_EL1
danh-arm
committed
on 28 Jul 2014
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Merge pull request #169 from achingupta/ag/tf-issues#198
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Ag/tf issues#198
danh-arm
committed
on 28 Jul 2014
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Rework incorrect use of assert() and panic() in codebase
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Assert a valid security state using the macro sec_state_is_valid().
Replace assert() with panic() in those cases that might arise
because of runtime errors and not programming errors.
Replace panic() with assert() in those cases that might arise
because of programming errors.
Fixes ARM-software/tf-issues#96
Change-Id: I51e9ef0439fd5ff5e0edfef49050b69804bf14d5
Juan Castillo
committed
on 28 Jul 2014
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Add CPUECTLR_EL1 and Snoop Control register to crash reporting
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This patch adds the CPUECTLR_EL1 register and the CCI Snoop Control
register to the list of registers being reported when an unhandled
exception occurs.
Change-Id: I2d997f2d6ef3d7fa1fad5efe3364dc9058f9f22c
Soby Mathew
committed
on 28 Jul 2014
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Rework the crash reporting in BL3-1 to use less stack
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This patch reworks the crash reporting mechanism to further
optimise the stack and code size. The reporting makes use
of assembly console functions to avoid calling C Runtime
to report the CPU state. The crash buffer requirement is
reduced to 64 bytes with this implementation. The crash
buffer is now part of per-cpu data which makes retrieving
the crash buffer trivial.
Also now panic() will use crash reporting if
invoked from BL3-1.
Fixes ARM-software/tf-issues#199
Change-Id: I79d27a4524583d723483165dc40801f45e627da5
Soby Mathew
committed
on 28 Jul 2014
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Implement an assert() callable from assembly code
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The patch implements a macro ASM_ASSERT() which can
be invoked from assembly code. When assertion happens,
file name and line number of the check is written
to the crash console.
Fixes ARM-software/tf-issues#95
Change-Id: I6f905a068e1c0fa4f746d723f18df60daaa00a86
Soby Mathew
committed
on 28 Jul 2014
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Introduce crash console APIs for crash reporting
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This patch introduces platform APIs to initialise and
print a character on a designated crash console.
For the FVP platform, PL011_UART0 is the designated
crash console. The platform porting guide is also updated
to document the new APIs.
Change-Id: I5e97d8762082e0c88c8c9bbb479353eac8f11a66
Soby Mathew
committed
on 28 Jul 2014
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Parametrize baudrate and UART clock during console_init()
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This patch adds baud rate and UART clock frequency as parameters
to the pl011 driver api console_init(). This allows each platform
to specify UART clock and baud rate according to their specific
hardware implementation.
Fixes ARM-software/tf-issues#215
Change-Id: Id13eef70a1c530e709b34dd1e6eb84db0797ced2
Soby Mathew
committed
on 28 Jul 2014
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Introduce asm console functions in TF
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This patch replaces the pl011 console family of functions
with their equivalents defined in assembly. The baud rate is
defined by the PL011_BAUDRATE macro and IBRD and FBRD values
for pl011 are computed statically. This patch will enable
us to invoke the console functions without the C Runtime Stack.
Change-Id: Ic3f7b7370ded38bf9020bf746b362081b76642c7
Soby Mathew
committed
on 28 Jul 2014
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Simplify management of SCTLR_EL3 and SCTLR_EL1
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This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.
Fixes ARM-software/tf-issues#226
Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
Achin Gupta
committed
on 28 Jul 2014
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Remove the concept of coherent stacks
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This patch removes the allocation of memory for coherent stacks, associated
accessor function and some dead code which called the accessor function. It also
updates the porting guide to remove the concept and the motivation behind using
stacks allocated in coherent memory.
Fixes ARM-software/tf-issues#198
Change-Id: I00ff9a04f693a03df3627ba39727e3497263fc38
Achin Gupta
committed
on 28 Jul 2014
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2014-07-25 |
Merge pull request #176 from danh-arm/jc/tf-issues/203-v3
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Add support for printing version at runtime v3
danh-arm
committed
on 25 Jul 2014
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Add support for printing version at runtime
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Print out Trusted Firmware version at runtime at each BL stage.
Message consists of TF version as defined statically in the Makefile
(e.g. v0.4), build mode (debug|release) and a customizable build
string:
1. By defining BUILD_STRING in command line when building TF
2. Default string is git commit ID
3. Empty if git meta-data is not available
Fixes ARM-software/tf-issues#203
Change-Id: I5c5ba438f66ab68810427d76b49c5b9177a957d6
Juan Castillo
authored
on 30 Jun 2014
Dan Handley
committed
on 25 Jul 2014
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