LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2017-11-06	Unverified 92c5066 Browse files » Merge pull request #1153 from robertovargas-arm/fix-macros ... Avoid use of undefined macros davidcunado-arm authored on 6 Nov 2017 GitHub committed on 6 Nov 2017
2017-11-03	Unverified f9a6db0 Browse files » Merge pull request #1151 from JoelHutton/jh/MISRA-Mandatory ... Change sizeof to use type of struct not function davidcunado-arm authored on 3 Nov 2017 GitHub committed on 3 Nov 2017
	Unverified 157650c Browse files » Merge pull request #1142 from etienne-lms/qemu-int ... qemu: update deprecated interrupt registering davidcunado-arm authored on 3 Nov 2017 GitHub committed on 3 Nov 2017
	Unverified 3de7d58 Browse files » Merge pull request #1137 from soby-mathew/sm/arm_plat_en_gicv3_save ... Enable GICv3 save for ARM platforms davidcunado-arm authored on 3 Nov 2017 GitHub committed on 3 Nov 2017
2017-11-02	ad3803b Browse files » qemu: update deprecated interrupt registering ... Registered interrupts are configured in edge detection as the default previous configuration assumed in previous code. Not target mask required as Qemu BL31 will not send/route SGIs. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 2 Nov 2017
2017-11-01	Unverified 122af7d Browse files » Merge pull request #1150 from dp-arm/dp/events ... aarch64: Add PubSub events to capture security state transitions davidcunado-arm authored on 1 Nov 2017 GitHub committed on 1 Nov 2017
	e8a87ac Browse files » Fix usage of IMAGE_BLx macros ... These macros are only defined for corresponding image, and they are undefined for other images. It means that we have to use ifdef or defined() instead of relying on being 0 by default. Change-Id: Iad11efab9830ddf471599b46286e1c56581ef5a7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com> Roberto Vargas committed on 1 Nov 2017
	d58f3ca Browse files » Always define ARM_TSP_RAM_LOCATION_ID ... ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro was also used in AARCH32, and it meant that it was taking the value 0, which happened to equal ARM_TRUSTED_SRAM_ID. Change-Id: If9f4dbee1a2ba15e7806f2a03305b554bd327363 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com> Roberto Vargas committed on 1 Nov 2017
	4d476e4 Browse files » Include debug.h in debug.S ... debug.S was using macros defined in debug.h, but since it didn't include it, these macros were taking the value 0, which means that all the preprocessor conditionals were wrong. Change-Id: If4ca81cc5a1662991589f914a2557ceff0eaaede Signed-off-by: Roberto Vargas <roberto.vargas@arm.com> Roberto Vargas committed on 1 Nov 2017
2017-10-31	Unverified 5b5e6cb Browse files » Merge pull request #1149 from robertovargas-arm/fwu-testing ... Add FWU booting instructions to the user guide davidcunado-arm authored on 31 Oct 2017 GitHub committed on 31 Oct 2017
	Unverified 27b2493 Browse files » Merge pull request #1141 from robertovargas-arm/boot_redundancy ... Add platform hooks for boot redundancy support davidcunado-arm authored on 31 Oct 2017 GitHub committed on 31 Oct 2017
	2614ea3 Browse files » Change sizeof to use type of struct not function ... Change sizeof call so it references a static type instead of return of a function in order to be MISRA compliant. Change-Id: I6f1adb206073d6cd200156e281b8d76249e3af0e Signed-off-by: Joel Hutton <joel.hutton@arm.com> Joel Hutton committed on 31 Oct 2017
	17b4c0d Browse files » aarch64: Add PubSub events to capture security state transitions ... Add events that trigger before entry to normal/secure world. The events trigger after the normal/secure context has been restored. Similarly add events that trigger after leaving normal/secure world. The events trigger after the normal/secure context has been saved. Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 31 Oct 2017
	e29ee46 Browse files » Add FWU booting instructions to the user guide ... FWU uses additional images that have to be loaded, and this patch adds the documentation of how to do it in FVP and Juno. Change-Id: I1a40641c11c5a4c8db0aadeaeb2bec30c9279e28 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com> Roberto Vargas committed on 31 Oct 2017
2017-10-30	Unverified a2ef56a Browse files » Merge pull request #1144 from geesun/qx/resize_bl2_size ... Change the default option of ARM_TSP_RAM_LOCATION and Enlarge the BL2 size on ARM platforms davidcunado-arm authored on 30 Oct 2017 GitHub committed on 30 Oct 2017
2017-10-26	2455224 Browse files » Merge pull request #1147 from etienne-lms/qemu-optee-load ... qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image davidcunado-arm authored on 26 Oct 2017 GitHub committed on 26 Oct 2017
	9071400 Browse files » Merge pull request #1143 from etienne-lms/qemu-hpen ... qemu: fix holding pen mailbox sequence davidcunado-arm authored on 26 Oct 2017 GitHub committed on 26 Oct 2017
	11d9b20 Browse files » qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image ... OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE secure RAM. To support this configuration the trusted firmware should not load OP-TEE resources in this area. To overcome the issue, OP-TEE pageable image is now loaded 2MByte above the secure RAM base address. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 26 Oct 2017
	cebec74 Browse files » Merge pull request #1138 from michpappas/tf-issues#526_qemu_does_not_support_TBB ... qemu: Add support for Trusted Board Boot davidcunado-arm authored on 26 Oct 2017 GitHub committed on 26 Oct 2017
2017-10-24	5cc34b1 Browse files » qemu: Add support for Trusted Board Boot ... This patch adds support for TBB to qemu. An RSA ROT keypair is generated at build time and is included into BL1/BL2. The key and content certificates are read over semihosting. Fixes ARM-software/tf-issues#526 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm> Michalis Pappas committed on 24 Oct 2017
	9b1eae9 Browse files » plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabled ... For Trusted Board Boot, BL2 needs more space to support the ECDSA and ECDSA+RSA algorithms. Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d Signed-off-by: Qixiang Xu <qixiang.xu@arm.com> Qixiang Xu committed on 24 Oct 2017
	7ca267b Browse files » plat/arm: change the default option of ARM_TSP_RAM_LOCATION ... On Arm standard platforms, it runs out of SRAM space when TBB is enabled, so the TSP default location is changed to dram when TBB is enabled. Change-Id: I516687013ad436ef454d2055d4e6fce06e467044 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com> Qixiang Xu committed on 24 Oct 2017
	01f62b6 Browse files » Add platform hooks for boot redundancy support ... These hooks are intended to allow one platform to try load images from alternative places. There is a hook to initialize the sequence of boot locations and a hook to pass to the next sequence. Change-Id: Ia0f84c415208dc4fa4f9d060d58476db23efa5b2 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com> Roberto Vargas committed on 24 Oct 2017
	33dd33f Browse files » qemu: fix holding pen mailbox sequence ... Before this change, plat_secondary_cold_boot_setup reads wake up mailbox as a byte array but through 64bit accesses on unaligned 64bit addresses. In the other hand qemu_pwr_domain_on wakes secondary cores by writing into a 64bit array. This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE explicitly specifies it. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 24 Oct 2017
2017-10-23	3b39efa Browse files » Merge pull request #1139 from hzhuang1/fix_edmac ... Fix edmac davidcunado-arm authored on 23 Oct 2017 GitHub committed on 23 Oct 2017
	4c37ac8 Browse files » Merge pull request #1132 from jeenu-arm/pubsub ... Publish and Subscribe framework davidcunado-arm authored on 23 Oct 2017 GitHub committed on 23 Oct 2017
	bd0c347 Browse files » PSCI: Publish CPU ON event ... This allows other EL3 components to subscribe to CPU on events. Update Firmware Design guide to list psci_cpu_on_finish as an available event. Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 23 Oct 2017
	8e743bc Browse files » BL31: Introduce Publish and Subscribe framework ... This light-weight framework enables some EL3 components to publish events which other EL3 components can subscribe to. Publisher can optionally pass opaque data for subscribers. The order in which subscribers are called is not defined. Firmware design updated. Change-Id: I24a3a70b2b1dedcb1f73cf48313818aebf75ebb6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 23 Oct 2017
2017-10-21	f911e22 Browse files » Merge pull request #1131 from jeenu-arm/gic-migrate ... Migrate upstream platforms to using interrupt properties davidcunado-arm authored on 21 Oct 2017 GitHub committed on 21 Oct 2017
2017-10-21	623c437 Browse files » Merge pull request #1130 from jeenu-arm/gic-patches ... New GIC APIs and specifying interrupt propertes davidcunado-arm authored on 21 Oct 2017 GitHub committed on 21 Oct 2017