xilinx: versal: Add get_api_version support ...

Add support for EEMI API get_api_verion.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic1ef90a194ae6164994a7fc5d8ff0b7b192636fe

xilinx: Add support to send PM API to PMC using IPI for versal ...

Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da

plat: xilinx: versal: Move versal_def.h to include directory ...

Move versal_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of versal_def.h

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91

plat: xilinx: versal: Move versal_private.h to include directory ...

Move versal_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I65eefbea7722ffa2760b992491c00eebef5bcef4

plat: xilinx: zynqmp: Use GIC framework for warm restart ...

- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts
  to be targeted to EL3.
- Raise SGI interrupts for individual CPU cores as GIC API
  uses CPU num as parameter, not CPU mask.
- Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable
  CPU interface mask work properly for all CPU cores which is
  required when generating SGI.
- Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear
  GIC interrupt to avoid same interrupt again.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7

plat: xilinx: zynqmp: Add checksum support for IPI data ...

This patch adds support for CRC checksum for IPI data when the
macro ZYNQMP_IPI_CRC_CHECK is defined.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic981f162666b3c1fffeb1b9fef3ee7714ecd889d

zynqmp: pm_service: Add support to query max divisor ...

Add new QID to get maximum supported divisor by clock.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a

zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node ...

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b

zynqmp: pm: clock: Move custom flags to typeflags ...

Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78

zynqmp: pm: clock: Add support for custom type flags ...

Add support to add extra custom type flags and provide
to caller in topology query.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40

plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function ...

Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81

zynqmp: pm: Remove CLK_TOPSW_LSBUS from invalid clock list ...

CLK_TOPSW_LSBUS is parent of WDT clock. Clock from invalid
clock list would not be registered to CCF framework and so
cannot be used as parent of other clocks.

WDT clock has default parent as CLK_TOPSW_LSBUS(APB clock).
If CLK_TOPSW_LSBUS is not registered, CCF would not recognize
that clock and hence rate of WDT clock would be calculated to
be 0 by CCF(as parent rate is considered 0).

So it is necessary to allow registration of CLK_TOPSW_LSBUS
clock.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iceaba0f137784fc5fd666e66ffc4c143381c6ccc

zynqmp: pm: Add LPD WDT clock to the pm_clock structure ...

This patch adds LPD WDT clock node to the pm_clock clocks structure list
so that LPD WDT can be used from Linux.

Also this patch removes the CLK_LPD_LSBUS from invalid clock list to
allow the registration of this clock to CCF framework as it is the
parent of LPD WDT.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Iea065aa8150eaba4bb4b42bc6be1fd4b7fe7b403

zynqmp: pm: Fix clock models and IDs of GEM-related clocks ...

GEM-related clock models were incorrect and are fixed as follows
(documented below for GEM0, but the same holds for any GEM ID):

- CLK_GEM0_REF_UNGATED represents clock that has DIV0/1 divisors and
 the multiplexer controllable in GEM0_REF_CTRL (CRL_APB). The ID of this
 clock is newly introduced in this patch.

- CLK_GEM0_REF models the clock mux that selects the reference clock
 for Tx, i.e. selects CLK_GEM0_REF_UNGATED or external Tx clock. This
 mux is controllable via GEM_CLK_CTRL (IOU_SLCR), bit GEM0_REF_SRC_SEL.
 Note that the routing of external clock to the mux is not modelled
 and is assumed to be configured by the FSBL if required, and not
 changeable at runtime. The ID of this clock is introduced in this patch.

- CLK_GEM0_TX models clock with only a gate that is controlled via
 bit 25 in GEM0_REF_CTRL (CRL_APB). The parent of this clock is
 CLK_GEM0_REF. The clock ID of CLK_GEM0_TX matches the previous ID
 value of CLK_GEM0_REF. This is done in order to fix the clock models
 and incorrect binding without requiring to change device-tree (binding
 of clock IDs to GEM interface).

- CLK_GEM0_RX models clock that has only gate controlled via RX_CLKACT
 bit (26) in GEM0_REF_CTRL (CRL_APB). Parent of this clock is sourced
 from external RGMII PHY (via MIO or EMIO). We do not model the whole
 clock path to the Rx gate, since this is configured by the FSBL and
 never changed at runtime (and there is no mechanism to change the
 path at runtime). The clock ID of CLK_GEM0_RX clock is equal to the
 previous ID value of CLK_GEM0_TX clock. This is done because the TX/RX
 were swapped in device tree, so by fixing the IDs this way there is no
 need for device tree fix.

Rates of the external RX/TX clocks can be specified in device tree if
needed. Right now, that's not necessary because Tx clock is sourced
from an on-chip PLL (via CLK_GEM0_REF_UNGATED/CLK_GEM0_REF), whereas
the Rx clock is sourced from external reference and the driver never
attempts to get/get clock rate (only to enable it). If this changes in
future, ATF clock model doesn't need to be changed. Instead, the clock
rates for gem0_tx_ext and gem0_rx_ext have to be specified in device
tree.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <will.wong@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I6497d4309e92205c527bd81b3aa932f4474f5b79

zynqmp: pm: Rename FPD WDT clock ID ...

This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c

plat: xilinx: zynqmp: Correct syscnt freq for QEMU ...

Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214

arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR ...

Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b
and 0x7e.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2978f16bb663853951ef8059bf0327f909447f34

arm64: zynqmp: Add id for new RFSoC device ZU39DR ...

This patch adds new RFSoC device ZU39DR to zynqmp
devices list

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d

Merge "drivers: add a driver for snoop control unit" into integration

drivers: add a driver for snoop control unit ...

The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.

The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
  processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
  L2 accesses
- manage ACP accesses.

Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.

This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT

Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

Merge "bl31: Split into two separate memory regions" into integration

Merge "mediatek: mt8183: add Vmodem/Vcore DVS init level" into integration

Merge "allwinner: Remove unused include path" into integration

Merge "rockchip: rk3328: Enable workaround for erratum 855873" into integration

Merge "Workaround for Hercules erratum 1688305" into integration

Merge "uniphier: run BL33 at EL2" into integration

allwinner: Remove unused include path ...

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95

bl31: Split into two separate memory regions ...

Some platforms are extremely memory constrained and must split BL31
between multiple non-contiguous areas in SRAM. Allow the NOBITS
sections (.bss, stacks, page tables, and coherent memory) to be placed
in a separate region of RAM from the loaded firmware image.

Because the NOBITS region may be at a lower address than the rest of
BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this
region, or el3_entrypoint_common would attempt to invalidate the dcache
for the entire address space. New symbols __NOBITS_{START,END}__ are
added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the
NOBITS region is invalidated separately.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37

uniphier: run BL33 at EL2 ...

All the SoCs in 64-bit UniPhier SoC family support EL2.

Just hard-code MODE_EL2 instead of using el_implemented() helper.

Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

mediatek: mt8183: add Vmodem/Vcore DVS init level ...

spm resume will restore Vmodem/Vcore voltages
back based on the SPM_DVS_LEVEL.

Change-Id: I37ff7ce4ba62219c1858acea816c5bc9ce6c493e
Signed-off-by: Roger Lu <roger.lu@mediatek.com>