LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-09-05	9a5616f Browse files » amlogic: Fix prefixes in the SCPI related code ... Add a new aml_* prefix to the SCPI related function calls. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I697812ac1c0df28cbb639a1dc3e838f1107fb739 Carlo Caione committed on 5 Sep 2019
	cbaad53 Browse files » amlogic: Fix prefixes in the MHU code ... Make the MHU code AML specific adding a new aml_* prefix and remove the GXBB prefix from the register names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2 Carlo Caione committed on 5 Sep 2019
	381b901 Browse files » amlogic: Fix prefixes in the SIP/SVC code ... All the SIP/SVC related code is currently the same between GXL and GXBB. Rename function names and register names to avoid hardcoding the GXBB prefix. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I7e58ab68489df8d4762663fc01fb64e6899cc8bf Carlo Caione committed on 5 Sep 2019
	73f6d05 Browse files » amlogic: Fix prefixes in the thermal driver ... No need to have a special SoC-specific prefix. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I0da543e7d92d56604e79440a98027ffd9a2eaa59 Carlo Caione committed on 5 Sep 2019
	010fdc1 Browse files » amlogic: Fix prefixes in the private header file ... The header file is shared between all the SoCs. Better avoiding hardcoding the SoC name in the function names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I9074871bd1ed8a702c1a656e0f50f2d3c6cb0425 Carlo Caione committed on 5 Sep 2019
	93c795a Browse files » amlogic: Fix prefixes in the efuse driver ... The efuse driver is hardcoding the GXBB prefix. No need to do that since the driver is shared between multiple SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I97691b0bbd55170d8216d301a3fc04feb8c2af2e Carlo Caione committed on 5 Sep 2019
	821781f Browse files » amlogic: Fix prefixes in the platform macros file ... Fixing at the same time the related register names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ib1130d50abe6088f1c0826878d1ae454a0f23008 Carlo Caione committed on 5 Sep 2019
	f681c67 Browse files » amlogic: Fix prefixes in the helpers file ... The code is the common directory is now generic, no need to have the SoC prefix hardcoded in the function names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ied3a5e506b9abd4c2d6f893bafef50019bff24f1 Carlo Caione committed on 5 Sep 2019
	fab6951 Browse files » amlogic: Rework Makefiles ... Now that every piece is in place, the makefiles can be refactored and slightly beautified removing useless and redundant parts. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: If74e1909df52d475cf4b0dfed819d07d3a4c85b9 Carlo Caione committed on 5 Sep 2019
	35aee24 Browse files » amlogic: Move the SIP SVC code to common directory ... The code is the same between GXBB and GXL. Move it to the common source directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I875689a6fd029971aa755fc2725217e90ed06b6c Carlo Caione committed on 5 Sep 2019
	261e7fd Browse files » amlogic: Move topology file to common directory ... As done already for multiple files, move the topology file to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Iaca357a089593ad58c35c05c929239132249dcda Carlo Caione committed on 5 Sep 2019
	cd94cc4 Browse files » amlogic: Move thermal code to common directory ... As for most of the Amlogic code, this is common between the Amlogic SoCs. Move the code to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Id3f0073ff1f0b9ddbe964f80303323ee4a2f27b0 Carlo Caione committed on 5 Sep 2019
	6f3b0dc Browse files » amlogic: Move MHU code to common directory ... The MHU code is shared between all the supported platforms. Move it to the common directory instead. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Iaf53122866eae85c13f772927d16836dcfa877a3 Carlo Caione committed on 5 Sep 2019
	d498d24 Browse files » amlogic: Move efuse code to common directory ... The efuse code is the same between GXL and GXBB. Move the code to common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ie37f21d1907a36292724f1fb645a78041fe4a6b3 Carlo Caione committed on 5 Sep 2019
	5b74369 Browse files » amlogic: Move platform macros assembly file to common directory ... The platform macros are shared between all the SoCs. Move it to common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ia04c3ffe4d7b068aa701268ed99f69995d8db92b Carlo Caione committed on 5 Sep 2019
	e26864a Browse files » amlogic: Introduce unified private header file ... Now that also the SHA256 DMA driver is shared between all the SoCs, we can have one single private platform header file. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I77d51915f9d8233aeceeed66ed1f491573402cfc Carlo Caione committed on 5 Sep 2019
	69b315a Browse files » amlogic: Move SCPI code to common directory ... The SCPI code is the same between GXBB and GXL. No need to have it replicated for each SoCs. Move it to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I7e416caf1e9538b3ce7702c0363ee00a054e2451 Carlo Caione committed on 5 Sep 2019
	01b2a7f Browse files » amlogic: Move the SHA256 DMA driver to common directory ... The SHA256 DMA driver can be used by multiple SoCs. Move it to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I96319eeeeeebd503ef0dcb07c0e4ff6a67afeaa5 Carlo Caione committed on 5 Sep 2019
	40fac1a Browse files » amlogic: Move assembly helpers to common directory ... The assembly helpers are common to all the amlogic SoCs. Move the .S file to the common directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I0d8616a7ae22dbcb14848cefd0149b6bb5814ea6 Carlo Caione committed on 5 Sep 2019
	1b25019 Browse files » amlogic: Introduce directory parameters in the makefiles ... Make the platform name a parameter for the source directories. Besides a cosmetic fix, this is going to be helpful when reusing the same Makefile for different SoCs. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I307897a21800cca8ad68a5ab8972d27e9356ff2a Carlo Caione committed on 5 Sep 2019
	4a079c7 Browse files » meson: Rename platform directory to amlogic ... Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d Carlo Caione committed on 5 Sep 2019
2019-08-28	3441952 Browse files » Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration Paul Beesley authored on 28 Aug 2019 TrustedFirmware Code Review committed on 28 Aug 2019
2019-08-27	de58048 Browse files » Merge "tegra: add support for multi console interface" into integration Sandrine Bailleux authored on 27 Aug 2019 TrustedFirmware Code Review committed on 27 Aug 2019
2019-08-23	3056091 Browse files » Merge "AArch64: Disable Secure Cycle Counter" into integration Paul Beesley authored on 23 Aug 2019 TrustedFirmware Code Review committed on 23 Aug 2019
2019-08-21	e290a8f Browse files » AArch64: Disable Secure Cycle Counter ... This patch fixes an issue when secure world timing information can be leaked because Secure Cycle Counter is not disabled. For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR_EL0.DP bit. 'include\aarch64\arch.h' header file was tided up and new ARMv8.5-PMU related definitions were added. Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 21 Aug 2019
2019-08-20	44e8d5e Browse files » Merge "plat/arm: Introduce corstone700 platform." into integration Paul Beesley authored on 20 Aug 2019 TrustedFirmware Code Review committed on 20 Aug 2019
	7cc287d Browse files » Merge "rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*" into integration Paul Beesley authored on 20 Aug 2019 TrustedFirmware Code Review committed on 20 Aug 2019
	7bdc469 Browse files » plat/arm: Introduce corstone700 platform. ... This patch adds support for Corstone-700 foundation IP, which integrates both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible subsystem. This is an example implementation of Corstone-700 IP host firmware. Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as bringing Host out RESET. Host will start execution directly from BL32 and then will jump to Linux. It is an initial port and additional features are expected to be added later. Change-Id: I7b5c0278243d574284b777b2408375d007a7736e Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 20 Aug 2019
	44f4bb2 Browse files » Merge "rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h" into integration Paul Beesley authored on 20 Aug 2019 TrustedFirmware Code Review committed on 20 Aug 2019
	bfc0c07 Browse files » Merge "intel: agilex: HMC driver calculate DDR size" into integration Paul Beesley authored on 20 Aug 2019 TrustedFirmware Code Review committed on 20 Aug 2019