LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-12-18	992f091 Browse files » debugfs: add SMC channel ... Provide an SMC interface to the 9p filesystem. This permits accessing firmware drivers through a common interface, using standardized read/write/control operations. Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I9314662314bb060f6bc02714476574da158b2a7d Ambroise Vincent authored on 12 Jul 2019 Olivier Deprez committed on 18 Dec 2019
2019-12-18	bb9549b Browse files » aarch64: Fix stack pointer maintenance on EA handling path ... EA handlers for exceptions taken from lower ELs at the end invokes el3_exit function. However there was a bug with sp maintenance which resulted in el3_exit setting runtime stack to context. This in turn caused memory corruption on consecutive EL3 entries. Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I0424245c27c369c864506f4baa719968890ce659 Jan Dabros committed on 18 Dec 2019
2019-12-17	e9e19fb Browse files » Tegra: per-CPU GIC CPU interface init ... This patch enables per-CPU GIC CPU interfaces during CPU power on. The previous code initialized the distributor for all CPUs, which was not required. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifd957b2367da06405b4c3e2225411adbaec35bb8 Varun Wadekar committed on 17 Dec 2019
	0d35873 Browse files » Merge changes from topic "allwinner_pmic" into integration ... * changes: allwinner: h6: power: Switch to using the AXP driver drivers: allwinner: axp: Add AXP805 support Soby Mathew authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
	4e0d14f Browse files » Merge "arm: gicv3: Fix compiler dependent behavior" into integration Soby Mathew authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
	287a81d Browse files » Merge "plat/rockchip: enable power domains of rk3399 before reset" into integration Soby Mathew authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
	37ebe8e Browse files » Merge "plat/rockchip: cliam a macro to enable hdcp feature for DP" into integration Soby Mathew authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
	0531ada Browse files » pmf: Make the runtime instrumentation work on AArch32 ... Ported the pmf asm macros and the asm code in the bl31 entrypoint necessary for the instrumentation to AArch32. Since smc dispatch is handled by the bl32 payload on AArch32, we provide this service only if AARCH32_SP=sp_min is set. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac Bence Szépkúti committed on 17 Dec 2019
	9d72519 Browse files » SiP: Don't validate entrypoint if state switch is impossible ... Switching execution states is only possible if EL3 is AArch64. As such there is no need to validate the entrypoint on AArch32 builds. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: I3c1eb25b5df296a492870641d274bf65213c6608 Bence Szépkúti committed on 17 Dec 2019
	7c58fd4 Browse files » intel: Fix SMC SIP service ... Fix FPGA reconfiguration driver logic Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0299c1a71f3456e9b441340314662494b8d3e4a0 Hadi Asyrafi committed on 17 Dec 2019
	96612fc Browse files » intel: Introduce mailbox response length handling ... Mailbox driver now handles variable response length Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ic96854fdaadaf48379c5de688392df974e1c99c3 Hadi Asyrafi committed on 17 Dec 2019
	b68ba6c Browse files » intel: Fix mailbox config return status ... Modify mailbox config return code to improve debugging. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0a223291f4c5296203b3295a679a5857a446c692 Hadi Asyrafi committed on 17 Dec 2019
	8014a53 Browse files » intel: Mailbox driver logic fixes ... Fix mailbox driver urgent command handling, doorbell routine, and logic optimization. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: If536a383f449ca2a68d60274303ec24f92411505 Hadi Asyrafi committed on 17 Dec 2019
	cefb37e Browse files » plat: intel: Fix FPGA manager on reconfiguration ... Fixes the SiP Service driver that is responsible for FPGA reconfiguration. Also change the base address of FPGA reconfiguration to 0x400000. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: I2b84c12c85cd5fc235247131fec4916ed2fb56c8 Tien Hock, Loh authored on 30 Oct 2019 Hadi Asyrafi committed on 17 Dec 2019
	68dd5e1 Browse files » plat: intel: Fix mailbox send_cmd issue ... There are a few issues in mailbox that needs to be fixed. - Send doorbell after an indirect cmd - Do not ring doorbell when polling mailbox response as it should've been sent by send_cmd - remove unneeded cmd_free_offset check - Fix mailbox initialization - Fix get_config_status returning a wrong status when the status is busy - Add command length in mailbox command header Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Change-Id: If613e2ca889a540a616c62d69ad0086a7cd46536 Tien Hock, Loh authored on 30 Oct 2019 Hadi Asyrafi committed on 17 Dec 2019
	d310239 Browse files » debugfs: add FIP device ... Add a FIP driver hooked to debugfs 9p interface. This is an abstraction of the FIP filesystem layer on top of a mass storage, or memory block driver. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: If275ea0824763de43ab666dab2a06de5352ff940 Olivier Deprez committed on 17 Dec 2019
	0ca3913 Browse files » debugfs: add 9p device interface ... The 9p interface provides abstraction layers allowing the software that uses devices to be independent from the hardware. This patch provides a file system abstraction to link drivers to their devices and propose a common interface to expose driver operations to higher layers. This file system can be used to access and configure a device by doing read/write operations. Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ia9662393baf489855dc0c8f389fe4a0afbc9c255 Olivier Deprez committed on 17 Dec 2019
	044b22a Browse files » Merge changes from topic "rockchip-secure-ddr" into integration ... * changes: rockchip: make miniloader ddr_parameter handling optional rockchip: px30: cleanup securing of ddr regions rockchip: px30: move secure init to separate file rockchip: really use base+size for secure ddr regions rockchip: bring TZRAM_SIZE values in line Sandrine Bailleux authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
	2f3abc1 Browse files » Merge changes from topic "allwinner_pmic" into integration ... * changes: allwinner: Convert AXP803 regulator setup code into a driver allwinner: a64: power: Use fdt_for_each_subnode allwinner: a64: power: Remove obsolete register check allwinner: a64: power: Remove duplicate DT check allwinner: Build PMIC bus drivers only in BL31 allwinner: a64: power: Make sunxi_turn_off_soc static allwinner: Merge duplicate code in sunxi_power_down allwinner: Clean up PMIC-related error handling allwinner: Synchronize PMIC enumerations allwinner: Enable clock before resetting I2C/RSB Sandrine Bailleux authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
	df5a968 Browse files » rockchip: make miniloader ddr_parameter handling optional ... Transfering the regions of ddr memory to additionally protect is very much specific to some rockchip internal first stage bootloader and doesn't get used in either mainline uboot or even Rockchip's published vendor uboot sources. This results in a big error ERROR: over or zero region, nr=0, max=10 getting emitted on every boot for most users and such a message coming from early firmware might actually confuse developers working with the system. As this mechanism seems to be only be used by Rockchip's internal miniloader hide it behind a build conditional, so it doesn't confuse people too much. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe Heiko Stuebner committed on 17 Dec 2019
	f55ef85 Browse files » rockchip: px30: cleanup securing of ddr regions ... So far the px30-related ddr security was loading data for regions to secure from a pre-specified memory location and also setting region0 to secure the first megabyte of memory in hard-coded setting (top=0, end=0, meaning 1MB). To make things more explicit and easier to read add a function doing the settings for specified memory areas, like other socs have and also add an assert to make sure any descriptor read from memory does not overlap the TZRAM security in region0 and TEE security in region1. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f Heiko Stuebner committed on 17 Dec 2019
	d2483af Browse files » rockchip: px30: move secure init to separate file ... Similar to others like rk3399 and rk3288 move the secure init to a separate file to unclutter the soc init a bit. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691 Heiko Stuebner committed on 17 Dec 2019
	52ff3b4 Browse files » Merge "doc: Fix indentation in build options documentation" into integration Olivier Deprez authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
	535fa66 Browse files » doc: Fix indentation in build options documentation ... Sphinx was showing the following warning message: docs/getting_started/build-options.rst:200: WARNING: Bullet list ends without a blank line; unexpected unindent. Change-Id: Iad5d49c1e0d25dd623ad15bce1af31babf860c03 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 17 Dec 2019
	985c8a3 Browse files » Merge "Update list of main maintainers" into integration Sandrine Bailleux authored on 17 Dec 2019 TrustedFirmware Code Review committed on 17 Dec 2019
2019-12-16	23f31d3 Browse files » intel: stratix10: Modify BL31 parameter handling ... Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I16118d791399f652b6d1093c10092935a3449c32 Hadi Asyrafi committed on 16 Dec 2019
	cf82aff Browse files » intel: Modify BL31 address mapping ... Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use of On-Chip RAM for BL31 specific variables filling down from handoff offset to reduce fragmentation Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099 Hadi Asyrafi committed on 16 Dec 2019
	2db1e76 Browse files » intel: stratix10: Enable uboot entrypoint support ... This patch will provide an entrypoint for uboot's spl into BL31. BL31 will also handle secondary cpu state during uboot's cold boot Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3 Hadi Asyrafi committed on 16 Dec 2019
	ec7d005 Browse files » intel: Modify mailbox's get_config_status ... Move the get_config_status out of sip_svc driver. Modify the function so that it can return either CONFIG_STATUS or RECONFIG_STATUS Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642d5900339e67f98be61380edc2b838e0dd47af Hadi Asyrafi committed on 16 Dec 2019
	d25041b Browse files » intel: Create SiP service header file ... Separate SiP related definition from mailbox header file Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4 Hadi Asyrafi committed on 16 Dec 2019