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History for arm-trusted-firmware / include / lib

2019-03-01	Unverified a4acc7f Browse files » Merge pull request #1751 from vwadekar/tegra-scatter-file-support ... Tegra scatter file support Antonio Niño Díaz authored on 1 Mar 2019 GitHub committed on 1 Mar 2019
	Unverified 37118a1 Browse files » Merge pull request #1849 from loumay-arm/lm/a73_errata ... Cortex-A73: Implement workaround for errata 852427 Antonio Niño Díaz authored on 1 Mar 2019 GitHub committed on 1 Mar 2019
	Unverified 4476838 Browse files » Merge pull request #1845 from ambroise-arm/av/errata ... Apply workarounds for errata of Cortex-A53, A55 and A57 Antonio Niño Díaz authored on 1 Mar 2019 GitHub committed on 1 Mar 2019
	Unverified dbd0bcf Browse files » Merge pull request #1848 from antonio-nino-diaz-arm/an/docs ... Minor changes to documentation and comments Antonio Niño Díaz authored on 1 Mar 2019 GitHub committed on 1 Mar 2019
2019-02-28	7330861 Browse files » Minor changes to documentation and comments ... Fix some typos and clarify some sentences. Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 28 Feb 2019
	25278ea Browse files » Cortex-A73: Implement workaround for errata 852427 ... In AArch32, execution of 2 instructions with opposite condition code might lead to either a data corruption or a CPU deadlock. Set the bit 12 of the Diagnostic Register to prevent this. Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 28 Feb 2019
	Unverified 64503b2 Browse files » Merge pull request #1839 from loumay-arm/lm/a7x_errata ... Cortex-A73/75/76 errata workaround Antonio Niño Díaz authored on 28 Feb 2019 GitHub committed on 28 Feb 2019
	0f6fbbd Browse files » Cortex-A57: Implement workaround for erratum 814670 ... Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Feb 2019
	6ab87d2 Browse files » Cortex-A55: Implement workaround for erratum 798797 ... Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Feb 2019
	a6cc661 Browse files » Cortex-A55: Implement workaround for erratum 778703 ... Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Feb 2019
	1afeee9 Browse files » Cortex-A55: Implement workaround for erratum 768277 ... Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Feb 2019
2019-02-27	c2ad38c Browse files » Tegra: Support for scatterfile for the BL31 image ... This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 27 Feb 2019
	5283962 Browse files » Add ARMv8.3-PAuth registers to CPU context ... ARMv8.3-PAuth adds functionality that supports address authentication of the contents of a register before that register is used as the target of an indirect branch, or as a load. This feature is supported only in AArch64 state. This feature is mandatory in ARMv8.3 implementations. This feature adds several registers to EL1. A new option called CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save them during Non-secure <-> Secure world switches. This option must be enabled if the hardware has the registers or the values will be leaked during world switches. To prevent leaks, this patch also disables pointer authentication in the Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will be trapped in EL3. Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 27 Feb 2019
	4d1ccf0 Browse files » Cleanup context handling library ... Minor style cleanup. Change-Id: Ief19dece41a989e2e8157859a265701549f6c585 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 27 Feb 2019
2019-02-26	5c6aa01 Browse files » Add workaround for errata 1073348 for Cortex-A76 ... Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 26 Feb 2019
	5cc8c7b Browse files » Add workaround for errata 1220197 for Cortex-A76 ... Streaming store under specific conditions might cause deadlock or data corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write streaming to the L2 to prevent this. Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 26 Feb 2019
	e6cab15 Browse files » Add workaround for errata 855423 of Cortex-A73 ... Broadcast maintainance operations might not be correctly synchronized between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this. Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 26 Feb 2019
2019-02-22	Unverified 3f995f3 Browse files » Merge pull request #1835 from jts-arm/rename ... Apply official names to new Arm Neoverse cores Antonio Niño Díaz authored on 22 Feb 2019 GitHub committed on 22 Feb 2019
2019-02-21	Unverified 5ba32a7 Browse files » Merge pull request #1828 from uarif1/master ... Introduce Versatile Express FVP platform to arm-trusted-firmware. Antonio Niño Díaz authored on 21 Feb 2019 GitHub committed on 21 Feb 2019
2019-02-19	c9fe6fe Browse files » ARMv7: support non-LPAE mapping (not xlat_v2) ... Support 32bit descriptor MMU table. This is required by ARMv7 architectures that do not support the Large Page Address Extensions. nonlpae_tables.c source file is dumped from the OP-TEE project: core_mmu_armv7.c and related header files. Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Usama Arif <usama.arif@arm.com> Etienne Carriere authored on 24 Oct 2017 Usama Arif committed on 19 Feb 2019
	11088e3 Browse files » Rename Cortex-Helios to Neoverse E1 ... Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 19 Feb 2019
	fd4bb0a Browse files » Rename Cortex-Helios filenames to Neoverse E1 ... Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 19 Feb 2019
	da6d75a Browse files » Rename Cortex-Ares to Neoverse N1 ... Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 19 Feb 2019
	b04ea14 Browse files » Rename Cortex-Ares filenames to Neoverse N1 ... Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 19 Feb 2019
2019-02-14	ff6f62e Browse files » Update macro to check need for CVE-2017-5715 mitigation ... Armv8.5 introduces the field CSV2 to register ID_AA64PFR0_EL1. It can have the following 3 values: - 0: Branch targets trained in one hardware described context may affect speculative execution in a different hardware described context. In some CPUs it may be needed to apply mitigations. - 1: Branch targets trained in one hardware described context can only affect speculative execution in a different hardware described context in a hard-to-determine way. No mitigation required. - 2: Same as 1, but the device is also aware of SCXTNUM_ELx register contexts. The TF doesn't use the registers, so there is no difference with 1. The field CSV2 was originally introduced in the TRM of the Cortex-A76 before the release of the Armv8.5 architecture. That TRM only mentions the meaning of values 0 and 1. Because of this, the code only checks if the field has value 1 to know whether to enable or disable the mitigations. This patch makes it aware of value 2 as well. Both values 1 and 2 disable the mitigation, and 0 enables it. Change-Id: I5af33de25a0197c98173f52c6c8c77b51a51429f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 14 Feb 2019
2019-02-11	1a74e4a Browse files » cpus: Add casts to all definitions in CPU headers ... There are some incorrect casts and some missing casts in the headers. This patch fixes the ones that were 64-bit or 32-bit wide wrongly and adds casts where they were missing. Note that none of the changes of the patch actually changes the values of the definitions. This patch is just for correctness. Change-Id: Iad6458021bad521922ce4f91bafff38b116b49eb Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 11 Feb 2019
2019-02-11	a69817e Browse files » cpus: Fix some incorrect definitions in CPU headers ... There are some values that should be 64-bit immediates but that resolve to 0 because the type of the value is 32-bit wide. This patch casts the expressions to 64-bit before the shift so that the definition has the correct value. The definitions are only used in assembly so far, so the code is not actually affected by this bug. The assembler treats all values as 64-bit values, so there are no overflows. Change-Id: I965e4be631c1d28787c0913661d224c82a6b9155 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 11 Feb 2019
2019-02-08	70b0f27 Browse files » libc: Move setjmp to libc folder ... Now that setjmp() and longjmp() are compliant with the standard they can be moved with the other libc files. Change-Id: Iea3b91c34eb353ace5e171e72f331602d57774d5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 8 Feb 2019
2019-01-31	Unverified 766ff01 Browse files » Merge pull request #1797 from antonio-nino-diaz-arm/an/remove-smccc-v2 ... Remove support for the SMC Calling Convention 2.0 Antonio Niño Díaz authored on 31 Jan 2019 GitHub committed on 31 Jan 2019
2019-01-30	0709055 Browse files » Remove support for the SMC Calling Convention 2.0 ... This reverts commit 2f370465241c ("Add support for the SMC Calling Convention 2.0"). SMCCC v2.0 is no longer required for SPM, and won't be needed in the future. Removing it makes the SMC handling code less complicated. The SPM implementation based on SPCI and SPRT was using it, but it has been adapted to SMCCC v1.0. Change-Id: I36795b91857b2b9c00437cfbfed04b3c1627f578 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 30 Jan 2019