Merge changes from topic "jc/coverity-fixes" into integration ...

* changes:
  Fix Coverity #261967, Infinite loop
  Fix Coverity #343017, Missing unlock
  Fix Coverity #343008, Side affect in assertion
  Fix Coverity #342970, Uninitialized scalar variable

Merge "spd: opteed: enable NS_TIMER_SWITCH" into integration

Merge changes from topic "intel-plat-refactor" into integration ...

* changes:
  intel: Platform common code refactor
  intel: Platform common code refactor

intel: Platform common code refactor ...

Pull out common code from aarch64 and include

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f

Merge changes from topic "qemu_sbsa" into integration ...

* changes:
  plat/qemu: add gicv3 support for qemu
  plat/qemu: move gicv2 codes to separate file

Fix Coverity #261967, Infinite loop ...

Coverity has identified that the __aeabi_imod function will loop forever
if the denominator is not a power of 2, which is probably not the
desired behaviour.

The functions in the rest of the file are compiler implementations of
division if ARMv7 does not implement division which is permitted by the
spec. However, while most of the functions in the file are documented
and referenced in other places online, __aeabi_uimod and __aeabi_imod
are not. For this reason, these functions have been removed from the
code base, which also removes the Coverity error.

Change-Id: I20066d72365329a8b03a5536d865c4acaa2139ae
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Fix Coverity #343017, Missing unlock ...

All other returns from this function unlock the responses_lock, so we
also should release the lock in this case.

Change-Id: Ie2cfa8755723fed79e809f9480190d11f373a217
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Fix Coverity #343008, Side affect in assertion ...

This patch simply splits off the increment of next_xlat into a separate
statement to ensure consistent behaviour if the assert was to ever be
removed.

Change-Id: I827f601ccea55f4da9442048419c9b8cc0c5d22e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Fix Coverity #342970, Uninitialized scalar variable ...

This ensures that probe_data starts with a reasonable default, as
opposed to whatever was left on the stack.

Change-Id: I5550efea5e2bec7717f9fa063cb11e6a7005cce5
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Merge "meson: gxl: Fix CPU hotplug" into integration

spd: opteed: enable NS_TIMER_SWITCH ...

Enable dispatcher to save/restore unbanked timer registers. So that
both secure (OP-TEE) and non-secure (Linux) worlds can have independent
access control over timer registers.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Change-Id: I4d58d5ff8298587ed478c8433fcbc3aef538d668

Merge "intel: stratix10: Fix BL31 memory mapping" into integration

Merge "meson: gxl: Fix reset and power off" into integration

intel: stratix10: Fix BL31 memory mapping ...

Previous config blocks ATF runtime service communications with SDM mailbox

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e

meson: gxl: Fix CPU hotplug ...

The CPU[1-3] are reset to initial/cold boot state (with their reset
address set to 0x0). In this state the cpus are waiting for another
one to set the reset address to bl31_warm_entrypoint and wake them up.

The CPU0 needs a bit of a workaround as changing the reset address
either through PSCI mailbox or the mmio mapped RVBAR (at 0xda834650)
does not seem to have any effect. Thus the workaround consists in
emulating the other CPUs' behavior with a WFE loop and manually jumping
to bl31_warm_entrypoint when woken back up by another one.

Change-Id: I11265620b5fd0619285e3993253a3f9a3ff6a7a4
Signed-off-by: Remi Pommarel <repk@triplefau.lt>

meson: gxl: Fix reset and power off ...

Before CPU enters standby state (wfi), the AP needs to signal the SCP
through PSCI mailbox.

Also at boot time the AP has to wait for the SCP to be ready before
sending the first scpi commands or it can crash.

Change-Id: Iacc99f5bec745ad71922c5ea07ca5b87088133b6
Signed-off-by: Remi Pommarel <repk@triplefau.lt>

Merge "Switch AARCH32/AARCH64 to __aarch64__" into integration

Merge "Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__" into integration

Switch AARCH32/AARCH64 to __aarch64__ ...

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>

Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ ...

NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>

Merge "doc: Suggest to use the latest version 8.3 of GCC" into integration

doc: Suggest to use the latest version 8.3 of GCC ...

At the time of writting, GCC 8.3-2019.03 is the latest version available
on developer.arm.com.

Switch to bare-metal toolchain (arm-eabi-) for AArch32. This allows to
have a finer control on the use of floating-point and SIMD instructions.

Change-Id: I4438401405eae1e5f6d531b0162e8fa06f69135e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

intel: Platform common code refactor ...

Pull out common code from agilex and stratix10

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc

Merge "intel: agilex: Fix BL31 memory mapping" into integration

Merge "Enable AMU for Cortex-Hercules" into integration

Enable AMU for Cortex-Hercules ...

Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>

Merge "uniphier: fix typo and coding style" into integration

Merge "uniphier: replace DIV_ROUND_UP() with div_round_up() from utils_def.h" into integration

Merge "rockchip: px30: Use new bl31_params_parse functions" into integration

uniphier: fix typo and coding style ...

Fix the typo "warn" -> "warm".

Also fix the following checkpatch.pl warnings:

  CHECK: Prefer using the BIT macro
  CHECK: No space is necessary after a cast
  CHECK: Alignment should match open parenthesis
  CHECK: Unnecessary parentheses around uniphier_io_policies[image_id].dev_handle

Change-Id: Ic11eea2668c4bf2d1e8f089e6338ba7b7156d80b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>