fdts: a5ds: cleanup enable-method in devicetree ...

Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.

Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

fdts: a5ds: add L2 cache node in devicetree ...

This change is to add L2 cache node into a5ds device tree.

Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

Merge "drivers: marvell: comphy-a3700: support SGMII COMPHY power off" into integration

Merge "drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2" into integration

Merge changes from topic "nonbl2-boot" into integration ...

* changes:
  intel: stratix10: Modify BL31 parameter handling
  intel: Modify BL31 address mapping
  intel: stratix10: Enable uboot entrypoint support

Merge "aarch64: Fix stack pointer maintenance on EA handling path" into integration

aarch64: Fix stack pointer maintenance on EA handling path ...

EA handlers for exceptions taken from lower ELs at the end invokes
el3_exit function. However there was a bug with sp maintenance which
resulted in el3_exit setting runtime stack to context. This in turn
caused memory corruption on consecutive EL3 entries.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0424245c27c369c864506f4baa719968890ce659

Merge changes from topic "allwinner_pmic" into integration ...

* changes:
  allwinner: h6: power: Switch to using the AXP driver
  drivers: allwinner: axp: Add AXP805 support

Merge "arm: gicv3: Fix compiler dependent behavior" into integration

Merge "plat/rockchip: enable power domains of rk3399 before reset" into integration

Merge "plat/rockchip: cliam a macro to enable hdcp feature for DP" into integration

Merge changes from topic "rockchip-secure-ddr" into integration ...

* changes:
  rockchip: make miniloader ddr_parameter handling optional
  rockchip: px30: cleanup securing of ddr regions
  rockchip: px30: move secure init to separate file
  rockchip: really use base+size for secure ddr regions
  rockchip: bring TZRAM_SIZE values in line

Merge changes from topic "allwinner_pmic" into integration ...

* changes:
  allwinner: Convert AXP803 regulator setup code into a driver
  allwinner: a64: power: Use fdt_for_each_subnode
  allwinner: a64: power: Remove obsolete register check
  allwinner: a64: power: Remove duplicate DT check
  allwinner: Build PMIC bus drivers only in BL31
  allwinner: a64: power: Make sunxi_turn_off_soc static
  allwinner: Merge duplicate code in sunxi_power_down
  allwinner: Clean up PMIC-related error handling
  allwinner: Synchronize PMIC enumerations
  allwinner: Enable clock before resetting I2C/RSB

rockchip: make miniloader ddr_parameter handling optional ...

Transfering the regions of ddr memory to additionally protect is very much
specific to some rockchip internal first stage bootloader and doesn't get
used in either mainline uboot or even Rockchip's published vendor uboot
sources.

This results in a big error
    ERROR:   over or zero region, nr=0, max=10
getting emitted on every boot for most users and such a message coming
from early firmware might actually confuse developers working with the
system.

As this mechanism seems to be only be used by Rockchip's internal miniloader
hide it behind a build conditional, so it doesn't confuse people too much.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe

rockchip: px30: cleanup securing of ddr regions ...

So far the px30-related ddr security was loading data for regions to secure
from a pre-specified memory location and also setting region0 to secure
the first megabyte of memory in hard-coded setting (top=0, end=0, meaning
1MB).

To make things more explicit and easier to read add a function doing
the settings for specified memory areas, like other socs have and also
add an assert to make sure any descriptor read from memory does not
overlap the TZRAM security in region0 and TEE security in region1.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f

rockchip: px30: move secure init to separate file ...

Similar to others like rk3399 and rk3288 move the secure init to a
separate file to unclutter the soc init a bit.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691

Merge "doc: Fix indentation in build options documentation" into integration

doc: Fix indentation in build options documentation ...

Sphinx was showing the following warning message:

docs/getting_started/build-options.rst:200: WARNING: Bullet list ends
without a blank line; unexpected unindent.

Change-Id: Iad5d49c1e0d25dd623ad15bce1af31babf860c03
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "Update list of main maintainers" into integration

intel: stratix10: Modify BL31 parameter handling ...

Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I16118d791399f652b6d1093c10092935a3449c32

intel: Modify BL31 address mapping ...

Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099

intel: stratix10: Enable uboot entrypoint support ...

This patch will provide an entrypoint for uboot's spl into BL31.
BL31 will also handle secondary cpu state during uboot's cold boot

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3

rockchip: really use base+size for secure ddr regions ...

The calls to secure ddr regions on rk3288 and rk3399 use parameters of
base and size - as it custom for specifying memory regions, but the
functions themself expect start and endpoints of the area.

This only works by chance for the TZRAM, as it starts a 0x0 and therefore
its end location is the same as its size.

To not fall into a trap later on adapt the functions to really take
base+size parameters.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab

rockchip: bring TZRAM_SIZE values in line ...

The agreed upon division of early boot locations is 0x40000 for bl31
to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot).

rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary
so pull the other platforms along to also give the Rockchip TF-A enough
room to comfortably live in.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f

Merge "libc: Fix SIZE_MAX on AArch32" into integration

libc: Fix SIZE_MAX on AArch32 ...

SIZE_MAX was mistakenly redefined from UINT32_MAX to UINT64_MAX
on AArch32 when the arch-specific headers were merged.

This value is not currently used by upstream TF-A source code,
so no functionality should be affected.

Change-Id: I2acf7f8736423697c7377e8ed4b08843ced26e66
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>

Merge "rockchip: Prevent macro expansion in paths" into integration

Merge "cryptocell: add cryptocell 712 RSA 3K support" into integration

Update list of main maintainers ...

Change-Id: Ia4faf873f8946992737f76870ac92bc5cb3f4020
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "Remove -Wpadded warning" into integration