2016-06-08 |
Merge pull request #639 from danh-arm/dh/import-libfdt
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Import libfdt v1.4.1 and related changes
danh-arm
committed
on 8 Jun 2016
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2016-06-07 |
Merge pull request #645 from sandrine-bailleux-arm/sb/improve-load-image-comments
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Update comments in load_image()
danh-arm
committed
on 7 Jun 2016
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Update comments in load_image()
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- Fix the function documentation.
Since commit 16948ae1, load_image() uses image IDs rather than image
names.
- Clarify the consequences of a null entry point argument.
- Slightly reorganize the code to remove an unnecessary 'if' statement.
Change-Id: Iebea3149a37f23d3b847a37a206ed23f7e8ec717
Sandrine Bailleux
committed
on 7 Jun 2016
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2016-06-06 |
Merge pull request #644 from sandrine-bailleux-arm/sb/rm-outdated-comment
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xlat lib: Remove out-dated comment
danh-arm
committed
on 6 Jun 2016
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2016-06-03 |
Merge pull request #641 from antonio-nino-diaz-arm/an/fvp-set-nv-ctr
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Implement plat_set_nv_ctr for FVP platforms
danh-arm
committed
on 3 Jun 2016
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Merge pull request #640 from sandrine-bailleux-arm/sb/fix-syntax-error
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Fix a syntax error in plat/arm/common/aarch64/arm_common.c
danh-arm
committed
on 3 Jun 2016
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Merge pull request #637 from yatharth-arm/yk/genfw-1134
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Add support for ARM Cortex-A73 MPCore Processor
danh-arm
committed
on 3 Jun 2016
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Merge pull request #636 from soby-mathew/sm/cpu_ctx_rem_aarch32_regs
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Build option to include AArch32 registers in cpu context
danh-arm
committed
on 3 Jun 2016
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Fix a syntax error
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Building TF with ERROR_DEPRECATED=1 fails because of a missing
semi-column. This patch fixes this syntax error.
Change-Id: I98515840ce74245b0a0215805f85c8e399094f68
Sandrine Bailleux
committed
on 3 Jun 2016
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Minor libfdt changes to enable TF integration
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* Move libfdt API headers to include/lib/libfdt
* Add libfdt.mk helper makefile
* Remove unused libfdt files
* Minor changes to fdt.h and libfdt.h to make them C99 compliant
Co-Authored-By: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I425842c2b111dcd5fb6908cc698064de4f77220e
Dan Handley
committed
on 3 Jun 2016
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Import libfdt v1.4.1
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Imports libfdt code from https://git.kernel.org/cgit/utils/dtc/dtc.git
tag "v1.4.1" commit 302fca9 .
Change-Id: Ia0d966058beee55a9047e80d8a05bbe4f71d8446
Dan Handley
committed
on 3 Jun 2016
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Exclude more files from checkpatch and checkcodebase
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Exclude documentation files from the `make checkcodebase` target
(these files were already excluded from checkpatch).
Also exclude libfdt files to prepare for import of this library.
Change-Id: Iee597ed66494de2b11cf84096f771f1f04472d5b
Dan Handley
committed
on 3 Jun 2016
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Move stdlib header files to include/lib/stdlib
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* Move stdlib header files from include/stdlib to include/lib/stdlib for
consistency with other library headers.
* Fix checkpatch paths to continue excluding stdlib files.
* Create stdlib.mk to define the stdlib source files and include directories.
* Include stdlib.mk from the top level Makefile.
* Update stdlib header path in the fip_create Makefile.
* Update porting-guide.md with the new paths.
Change-Id: Ia92c2dc572e9efb54a783e306b5ceb2ce24d27fa
Dan Handley
committed
on 3 Jun 2016
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Implement plat_set_nv_ctr for FVP platforms
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Replaced placeholder implementation of plat_set_nv_ctr for FVP
platforms by a working one.
On FVP, the mapping of region DEVICE2 has been changed from RO to RW
to prevent exceptions when writing to the NV counter, which is
contained in this region.
Change-Id: I56a49631432ce13905572378cbdf106f69c82f57
Antonio Nino Diaz
committed
on 3 Jun 2016
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Build option to include AArch32 registers in cpu context
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The system registers that are saved and restored in CPU context include
AArch32 systems registers like SPSR_ABT, SPSR_UND, SPSR_IRQ, SPSR_FIQ,
DACR32_EL2, IFSR32_EL2 and FPEXC32_EL2. Accessing these registers on an
AArch64-only (i.e. on hardware that does not implement AArch32, or at
least not at EL1 and higher ELs) platform leads to an exception. This patch
introduces the build option `CTX_INCLUDE_AARCH32_REGS` to specify whether to
include these AArch32 systems registers in the cpu context or not. By default
this build option is set to 1 to ensure compatibility. AArch64-only platforms
must set it to 0. A runtime check is added in BL1 and BL31 cold boot path to
verify this.
Fixes ARM-software/tf-issues#386
Change-Id: I720cdbd7ed7f7d8516635a2ec80d025f478b95ee
Soby Mathew
committed
on 3 Jun 2016
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2016-06-02 |
xlat lib: Remove out-dated comment
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As of commit e1ea9290bb, if the attributes of an inner memory region
are different than the outer region, new page tables are generated
regardless of how "restrictive" they are. This patch removes an
out-dated comment still referring to the old priority system based
on which attributes were more restrictive.
Change-Id: Ie7fc1629c90ea91fe50315145f6de2f3995e5e00
Sandrine Bailleux
committed
on 2 Jun 2016
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2016-06-01 |
Add support for ARM Cortex-A73 MPCore Processor
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This patch adds ARM Cortex-A73 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.
Change-Id: I0e26b594f2ec1d28eb815db9810c682e3885716d
Yatharth Kochar
committed
on 1 Jun 2016
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2016-05-27 |
Merge pull request #632 from rockchip-linux/support-for-gpio-driver-v2
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rockchip/rk3399: Support the gpio driver and configure
danh-arm
committed
on 27 May 2016
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Merge pull request #634 from sandrine-bailleux-arm/sb/exception-vectors
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Improve robustness and readability of exception code
danh-arm
committed
on 27 May 2016
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Merge pull request #633 from soby-mathew/sm/psci_wfi_hook
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PSCI: Add pwr_domain_pwr_down_wfi() hook in plat_psci_ops
danh-arm
committed
on 27 May 2016
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Merge pull request #627 from soby-mathew/sm/fvp_ccn502_sup_1
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Add CCN support to FVP
danh-arm
committed
on 27 May 2016
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2016-05-26 |
rockchip: support system off function for rk3399
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if define power off gpio, BL31 will do system power off through
gpio control.
Caesar Wang
committed
on 26 May 2016
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rockchip: support reset SoC through gpio for rk3399
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If define a reset gpio, BL31 will use gpio to reset SOC,
otherwise use CRU reset.
Caesar Wang
committed
on 26 May 2016
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rockchip: add reset or power off gpio configuration for rk3399
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We add plat parameter structs to support BL2 to pass variable-length,
variable-type parameters to BL31. The parameters are structured as a
link list. During bl31 setup time, we travse the list to process each
parameter. throuth this way, we can get the reset or power off gpio
parameter, and do hardware control in BL31. This structure also can
pass other parameter to BL31 in future.
Caesar Wang
committed
on 26 May 2016
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rockchip: support rk3399 gpio driver
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There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-programmable.
At the moment, we add the gpio basic driver since reset or power off
the devices from gpio configuration for BL31.
Caesar Wang
committed
on 26 May 2016
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gpio: support gpio set/get pull status
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On some platform gpio can set/get pull status when input, add these
function so we can set/get gpio pull status when need it. And they are
optional function.
Caesar Wang
committed
on 26 May 2016
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Fill exception vectors with zero bytes
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The documentation of the GNU assembler specifies the following about
the .align assembler directive:
"the padding bytes are normally zero. However, on some systems, if
the section is marked as containing code and the fill value is
omitted, the space is filled with no-op instructions."
(see https://sourceware.org/binutils/docs/as/Align.html)
When building Trusted Firmware, the AArch64 GNU assembler uses a
mix of zero bytes and no-op instructions as the padding bytes to
align exception vectors.
This patch mandates to use zero bytes to be stored in the padding
bytes in the exception vectors. In the AArch64 instruction set, no
valid instruction encodes as zero so this effectively inserts
illegal instructions. Should this code end up being executed for
any reason, it would crash immediately. This gives us an extra
protection against misbehaving code at no extra cost.
Change-Id: I4f2abb39d0320ca0f9d467fc5af0cb92ae297351
Sandrine Bailleux
committed
on 26 May 2016
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Introduce some helper macros for exception vectors
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This patch introduces some assembler macros to simplify the
declaration of the exception vectors. It abstracts the section
the exception code is put into as well as the alignments
constraints mandated by the ARMv8 architecture. For all TF images,
the exception code has been updated to make use of these macros.
This patch also updates some invalid comments in the exception
vector code.
Change-Id: I35737b8f1c8c24b6da89b0a954c8152a4096fa95
Sandrine Bailleux
committed
on 26 May 2016
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2016-05-25 |
PSCI: Add pwr_domain_pwr_down_wfi() hook in plat_psci_ops
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This patch adds a new optional platform hook `pwr_domain_pwr_down_wfi()` in
the plat_psci_ops structure. This hook allows the platform to perform platform
specific actions including the wfi invocation to enter powerdown. This hook
is invoked by both psci_do_cpu_off() and psci_cpu_suspend_start() functions.
The porting-guide.md is also updated for the same.
This patch also modifies the `psci_power_down_wfi()` function to invoke
`plat_panic_handler` incase of panic instead of the busy while loop.
Fixes ARM-Software/tf-issues#375
Change-Id: Iba104469a1445ee8d59fb3a6fdd0a98e7f24dfa3
Soby Mathew
committed
on 25 May 2016
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Add CCN support to FVP platform port
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This patch adds support to select CCN driver for FVP during build.
A new build option `FVP_INTERCONNECT_DRIVER` is added to allow
selection between the CCI and CCN driver. Currently only the CCN-502
variant is supported on FVP.
The common ARM CCN platform helper file now verifies the cluster
count declared by platform is equal to the number of root node
masters exported by the ARM Standard platform.
Change-Id: I71d7b4785f8925ed499c153b2e9b9925fcefd57a
Soby Mathew
committed
on 25 May 2016
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