Tegra: support to set the L2 ECC and Parity enable bit ...

This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.

* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4

Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: console clock settings for real/FPGA platforms ...

This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.

Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: platform: helper functions to read chip ID ...

This patch adds helper functions to find out the chip ID of the
Tegra SoC.

Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: retrieve power domain tree from the platforms ...

The platform code generates the power domain tree. The handler to
retrieve the tree should also reside in the platform code.

This patch moves the plat_get_power_domain_tree_desc() to the
individual platforms.

Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: platform: support simulation platforms and MISRA fixes ...

This patch adds support for simulation platforms as well as
fixes issues flagged by the MISRA scans.

Main MISRA fixes:

* Added explicit casts (e.g. 0U) to integers in order for them to be
  compatible with whatever operation they're used in [Rule 10.1]
* Fix return type doesn't match the function type [Rule 10.3]
* Use single return point instead of multiple [Rule 15.5]
* Change return type for the tegra_platform_is_x handlers to bool

Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Merge pull request #1738 from ardbiesheuvel/synquacer-spm ...

synquacer: add SPM support

Merge pull request #1757 from antonio-nino-diaz-arm/an/includes ...

Move BL1 and BL2 private defines to bl_common.h

Merge pull request #1755 from Anson-Huang/lpuart ...

make lpuart and imx uart work for debug mode

Merge pull request #1758 from pbeesley-arm/pb/spelling ...

Correct typographical errors

Merge pull request #1756 from antonio-nino-diaz-arm/an/header-deps ...

plat/arm: Fix header dependencies

plat/synquacer: enable SPM support ...

Enable the deprecated SPM framework for the SynQuacer platform.
It involves creating a memory layout in secure DRAM, and wiring
up the SPM infrastructure so that the secure partition payload
that is loaded into this region by the SCP firmware is dispatched
appropriately.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

plat/synquacer: enable OP-TEE logic only if SPD_opteed is set ...

The logic that initializes the BL32 entry point data structure
should only be executed if we are in fact loading OP-TEE, and
not if BL32_BASE is set for other reasons (i.e., when enabling
SPM)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

spm: permit platform to override the VMA placement of the vector table ...

On some systems, it may be preferred to place the secure EL1/0 vector
table outside of the static placement of the BL31 image itself, for
instance when the latter is located in non-shareable SRAM which does
not tolerate inner shareable WBWA mappings (as is the case on SynQuacer)

So permit the platform to #define SPM_SHIM_EXCEPTIONS_VMA in its
supplementary linker script, in which case it will be used as the
VMA region for the vector table. Note that the LMA does not change,
and it is up to the platform to copy the contents to the right place
at init time.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

services/spm_deprecated: fix return code polarity of spm_init() ...

Registered init handlers return a boolean int, not a return code,
so convert the result from the SPM init call before returning it.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

services/spm_deprecated: disable alignment checking for S-EL0 ...

Permit unaligned accesses while executing the secure partition
payload, so that we don't have to modify existing code that we
will host there. (The UEFI spec explicitly permits unaligned
accesses)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Correct typographical errors ...

Corrects typos in core code, documentation files, drivers, Arm
platforms and services.

None of the corrections affect code; changes are limited to comments
and other documentation.

Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

plat/arm: Fix header dependencies ...

From now on, platform_def.h must include any header with definitions that
are platform-specific (like arm_def.h) and the included headers mustn't
include back platform_def.h, and shouldn't be used by other files. Only
platform_def.h should be included in other files. This will ensure that all
needed definitions are present, rather than needing to include all the
headers in all the definitions' headers just in case.

This also prevents problems like cyclic dependencies.

Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Move BL1 and BL2 private defines to bl_common.h ...

The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for
platforms that may need to access them.

Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1748 from antonio-nino-diaz-arm/an/build-flags ...

build: Support BL-specific build flags

Merge pull request #1747 from antonio-nino-diaz-arm/an/cnp-dynamic ...

xlat v2: Dynamically detect need for CnP bit

Merge pull request #1746 from JoelHutton/jh/hikey ...

Jh/hikey

Merge pull request #1752 from JackyBai/master ...

maintainers: Add maintainter for NXP i.MX8M platform.

Merge pull request #1750 from pbeesley-arm/pb/readme-updates ...

doc: Minor reword & reformatting in readme.rst

imx: make imx uart work for debug mode ...

With DEBUG_CONSOLE enabled, build will fail for imx8mq platform:

./build/imx8mq/release/bl31/imx8mq_bl31_setup.o:
In function `bl31_early_platform_setup2':
imx8mq_bl31_setup.c:(.text.bl31_early_platform_setup2+0x40):
	undefined reference to `console_uart_register'
Makefile:741: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed
make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1

Besides, the .console_flush callback needs to be added to avoid
panic when debug mode is enabled, since the console_flush() will
call it without checking whether the function callback is valid.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

imx: add necessary lpuart console_flush callback for debug ...

Current lpuart driver does NOT implement .console_flush callback,
if debug console is enabled, the console_flush() will call the
undefined .console_flush callback(NULL) for lpuart and leak to
panic, this patch adds .console_flush callback to make lpuart work
for debug mode.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

maintainers: Add maintainter for NXP i.MX8M platform. ...

This patch adds me to various maintainer activities in
the ATF tree associated with the NXP i.MX8M platform.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>

doc: Minor readme structure improvements ...

Improves wording and sentence structure of the readme, including:

- Using "TF-A" in place of "the TF-A" in a couple of places
- "Support for X" in place of "Support X"
- Explicitly naming the Secure Payload Dispatcher when introducing the
  SPD acronym.

Change-Id: I4e7b7e7dc6748f631d07c02d97adcca10ae60ea4
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

doc: Fix NVIDIA name case in readme.rst ...

Change-Id: I7e0ba692277c1c120c86d47ab966dcd11682428a
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

doc: Add SCMI abbreviation to readme ...

Currently the examples of Arm interface standards all include
abbreviationsof the full names, except for SCMI.

Change-Id: I8417ada780d51ecf93426aa5d265c507c7dac08c
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

xlat v2: Dynamically detect need for CnP bit ...

ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented
in CPUs that don't implement all mandatory 8.2 features (and so have to
claim to be a lower version).

This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system
ID registers to detect whether it is needed to set the bit or not.

Change-Id: I7bcbf0c7c937590dfc2ca668cfd9267c50f7d52c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>