2019-12-17 |
Merge changes from topic "allwinner_pmic" into integration
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* changes:
allwinner: Convert AXP803 regulator setup code into a driver
allwinner: a64: power: Use fdt_for_each_subnode
allwinner: a64: power: Remove obsolete register check
allwinner: a64: power: Remove duplicate DT check
allwinner: Build PMIC bus drivers only in BL31
allwinner: a64: power: Make sunxi_turn_off_soc static
allwinner: Merge duplicate code in sunxi_power_down
allwinner: Clean up PMIC-related error handling
allwinner: Synchronize PMIC enumerations
allwinner: Enable clock before resetting I2C/RSB
Sandrine Bailleux
authored
on 17 Dec 2019
TrustedFirmware Code Review
committed
on 17 Dec 2019
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rockchip: make miniloader ddr_parameter handling optional
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Transfering the regions of ddr memory to additionally protect is very much
specific to some rockchip internal first stage bootloader and doesn't get
used in either mainline uboot or even Rockchip's published vendor uboot
sources.
This results in a big error
ERROR: over or zero region, nr=0, max=10
getting emitted on every boot for most users and such a message coming
from early firmware might actually confuse developers working with the
system.
As this mechanism seems to be only be used by Rockchip's internal miniloader
hide it behind a build conditional, so it doesn't confuse people too much.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe
Heiko Stuebner
committed
on 17 Dec 2019
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rockchip: px30: cleanup securing of ddr regions
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So far the px30-related ddr security was loading data for regions to secure
from a pre-specified memory location and also setting region0 to secure
the first megabyte of memory in hard-coded setting (top=0, end=0, meaning
1MB).
To make things more explicit and easier to read add a function doing
the settings for specified memory areas, like other socs have and also
add an assert to make sure any descriptor read from memory does not
overlap the TZRAM security in region0 and TEE security in region1.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f
Heiko Stuebner
committed
on 17 Dec 2019
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rockchip: px30: move secure init to separate file
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Similar to others like rk3399 and rk3288 move the secure init to a
separate file to unclutter the soc init a bit.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Iebb38e24f1c7fe5353f139c896fb8ca769bf9691
Heiko Stuebner
committed
on 17 Dec 2019
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Merge "doc: Fix indentation in build options documentation" into integration
Olivier Deprez
authored
on 17 Dec 2019
TrustedFirmware Code Review
committed
on 17 Dec 2019
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doc: Fix indentation in build options documentation
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Sphinx was showing the following warning message:
docs/getting_started/build-options.rst:200: WARNING: Bullet list ends
without a blank line; unexpected unindent.
Change-Id: Iad5d49c1e0d25dd623ad15bce1af31babf860c03
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 17 Dec 2019
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Merge "Update list of main maintainers" into integration
Sandrine Bailleux
authored
on 17 Dec 2019
TrustedFirmware Code Review
committed
on 17 Dec 2019
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2019-12-16 |
intel: stratix10: Modify BL31 parameter handling
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Add-in support for handling BL31 parameter from non-BL2 image, ie. SPL
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I16118d791399f652b6d1093c10092935a3449c32
Hadi Asyrafi
committed
on 16 Dec 2019
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intel: Modify BL31 address mapping
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Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
Hadi Asyrafi
committed
on 16 Dec 2019
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intel: stratix10: Enable uboot entrypoint support
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This patch will provide an entrypoint for uboot's spl into BL31.
BL31 will also handle secondary cpu state during uboot's cold boot
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I661bdb782c2d793d5fc3c7f78dd7ff746e33b7a3
Hadi Asyrafi
committed
on 16 Dec 2019
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intel: Modify mailbox's get_config_status
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Move the get_config_status out of sip_svc driver.
Modify the function so that it can return either
CONFIG_STATUS or RECONFIG_STATUS
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642d5900339e67f98be61380edc2b838e0dd47af
Hadi Asyrafi
committed
on 16 Dec 2019
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intel: Create SiP service header file
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Separate SiP related definition from mailbox header file
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45ba540f29d9261007f7ec23469358747cf140b4
Hadi Asyrafi
committed
on 16 Dec 2019
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rockchip: really use base+size for secure ddr regions
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The calls to secure ddr regions on rk3288 and rk3399 use parameters of
base and size - as it custom for specifying memory regions, but the
functions themself expect start and endpoints of the area.
This only works by chance for the TZRAM, as it starts a 0x0 and therefore
its end location is the same as its size.
To not fall into a trap later on adapt the functions to really take
base+size parameters.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab
Heiko Stuebner
committed
on 16 Dec 2019
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rockchip: bring TZRAM_SIZE values in line
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The agreed upon division of early boot locations is 0x40000 for bl31
to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot).
rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary
so pull the other platforms along to also give the Rockchip TF-A enough
room to comfortably live in.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f
Heiko Stuebner
committed
on 16 Dec 2019
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Merge "libc: Fix SIZE_MAX on AArch32" into integration
György Szing
authored
on 16 Dec 2019
TrustedFirmware Code Review
committed
on 16 Dec 2019
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libc: Fix SIZE_MAX on AArch32
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SIZE_MAX was mistakenly redefined from UINT32_MAX to UINT64_MAX
on AArch32 when the arch-specific headers were merged.
This value is not currently used by upstream TF-A source code,
so no functionality should be affected.
Change-Id: I2acf7f8736423697c7377e8ed4b08843ced26e66
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Bence Szépkúti
committed
on 16 Dec 2019
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Merge "rockchip: Prevent macro expansion in paths" into integration
Sandrine Bailleux
authored
on 16 Dec 2019
TrustedFirmware Code Review
committed
on 16 Dec 2019
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Merge "cryptocell: add cryptocell 712 RSA 3K support" into integration
Soby Mathew
authored
on 16 Dec 2019
TrustedFirmware Code Review
committed
on 16 Dec 2019
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Update list of main maintainers
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Change-Id: Ia4faf873f8946992737f76870ac92bc5cb3f4020
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Sandrine Bailleux
committed
on 16 Dec 2019
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Merge "Remove -Wpadded warning" into integration
Sandrine Bailleux
authored
on 16 Dec 2019
TrustedFirmware Code Review
committed
on 16 Dec 2019
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Remove -Wpadded warning
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-Wpadded warns whenever the C compiler automatically includes any
padding in a structure. Because TF-A has a large number of structures,
this occurs fairly frequently and is incredibly verbose, and as such is
unlikely to ever be fixed.
The utility of this warning is also extremely limited - knowing that a
structure includes padding does not point to the existence of an error,
and is probably quite unlikely to indicate actually buggy behaviour.
Therefore, it's probably best to keep this warning off at all times.
Change-Id: I0797cb75f06b4fea0d2fdc16fd5ad978a31d76ec
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Justin Chadwell
authored
on 18 Sep 2019
Sandrine Bailleux
committed
on 16 Dec 2019
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Merge "Remove -Wmissing-declarations warning from WARNING1 level" into integration
Sandrine Bailleux
authored
on 16 Dec 2019
TrustedFirmware Code Review
committed
on 16 Dec 2019
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2019-12-13 |
allwinner: h6: power: Switch to using the AXP driver
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Chip ID checking and poweroff work just like they did before.
Regulators are now enabled just like on A64/H5.
This changes the signatures of the low-level register read/write
functions to match the interface expected by the common driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I14d63d171a094fa1375904928270fa3e21761646
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Convert AXP803 regulator setup code into a driver
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Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.
Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.
I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.
The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
Samuel Holland
committed
on 13 Dec 2019
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drivers: allwinner: axp: Add AXP805 support
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This adds the new regulator list, as well as changes to make the switch
(equivalent to DC1SW on the AXP803) work on both PMICs.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I9a1eac8ddfc54b27096c10a8eebdd51aaf9b8311
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Use fdt_for_each_subnode
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This simplifies the code a bit. Verified to produce the same binary.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Remove obsolete register check
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As of a561e41bf1d2 ("allwinner: power: add enable switches for DCDC1/5")
there are no longer regulators without an enable register provided.
Since it seems reasonable that this will continue to be the case, drop
the check.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icd7ec26fc6450d053e6e6d855fc16229b1d65a39
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Remove duplicate DT check
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should_enable_regulator() is already checked in the regulators subnode
loop before setup_regulator() is called, so there's no need to check it
again here.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idb8b8a6e435246f4fb226bc84813449d80a0a977
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Build PMIC bus drivers only in BL31
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These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed before BL31, or it wouldn't be possible to boot.
Allwinner platforms don't generally build anything but BL31 anyway, but
this change improves clarity and consistency with allwinner-common.mk.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Make sunxi_turn_off_soc static
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The function is only used in this file, and it doesn't make sense for it
to be used anywhere else.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iab18f082911edcdbc37ceeaff8c512be68e0cb0f
Samuel Holland
committed
on 13 Dec 2019
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