allwinner: Synchronize PMIC enumerations ...

Ensure that the default (zero) value represents the case where we take
no action. Previously, if a PLAT=sun50i_a64 build was booted on an
unknown SoC ID, it would be treated as an H5 at shutdown.

This removes some duplicate code and fixes error propagation on H6.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I4e51d8a43a56eccb0d8088593cb9908e52e782bc

allwinner: Enable clock before resetting I2C/RSB ...

The clock must be running for the module to be reset.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a

Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration

Merge changes from topic "aa/sel2_support" into integration ...

* changes:
  S-EL2 Support: Check for AArch64
  Add support for enabling S-EL2

Merge "allwinner: power: Add DLDO4 power rail" into integration

Merge "intel: s10: Remove unused source code" into integration

Merge changes from topic "enable-tegra194-compilation" into integration ...

* changes:
  docs: tegra: add support for Tegra194 class of SoCs
  Tegra194: smmu: add support for backup multiple smmu regs
  Tegra194: introduce tegra_mc_def.h
  Tegra194: 40-bit wide memory address space
  Tegra194: psci: rename 'percpu_data' variable

Merge "PIE: make call to GDT relocation fixup generalized" into integration

PIE: make call to GDT relocation fixup generalized ...

When a Firmware is complied as Position Independent Executable it needs
to request GDT fixup by passing size of the memory region to
el3_entrypoint_common macro.
The Global descriptor table fixup will be done early on during cold boot
process of primary core.

Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be
compiled as PIE, it can simply pass fixup size to the common el3
entrypoint macro to fixup GDT.

The reason for this patch was to overcome the bug introduced by SHA
330ead806 which called fixup routine for each core causing
re-initializing of global pointers thus overwriting any changes
done by the previous core.

Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

intel: s10: Remove unused source code ...

remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory
as both has been refactored to common directory for sharing with agilex
platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I395fed66408f536e8fefd637681e742c63621818

Merge "libc: add memrchr" into integration

libc: add memrchr ...

This function scans a string backwards from the end for the first
instance of a character.

Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

docs: tegra: add support for Tegra194 class of SoCs ...

This patch adds the Tegra194 SoC information to the nvidia-tegra.rst
file.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454

Tegra194: smmu: add support for backup multiple smmu regs ...

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.

Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: introduce tegra_mc_def.h ...

This patch introduces memory controller register defines
for Tegra194 platforms.

Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: 40-bit wide memory address space ...

This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.

Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra194: psci: rename 'percpu_data' variable ...

The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspelt.

This patch fixes this typographical error to fix compilation errors.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735

Merge "adding support to enable different personality of the same soc." into integration

Merge "Use the proper size for tb_fw_cfg_dtb" into integration

Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integration

arm: Fix current RECLAIM_INIT_CODE behavior ...

Previously the .init section was created even when the reclaim flag was
manually set to 0.

Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
	       Zelalem Aweke <zelalem.aweke@arm.com>

Merge changes from topic "lm/memmap" into integration ...

* changes:
  Add memory_map tools as a target for Make
  tools: Add show_memory script

Use the proper size for tb_fw_cfg_dtb ...

Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page
(but depend on the platform). Instead, read the actual size of the dtb
with the libfdt "fdt_totalsize" function.
This avoid flushing extra memory after updating the dtb with mbedtls
heap information when shared heap is used.

Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

S-EL2 Support: Check for AArch64 ...

Check that entry point information requesting S-EL2
has AArch64 as an execution state during context setup.

Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7

Add support for enabling S-EL2 ...

This patch adds support for enabling S-EL2 if this EL is specified in the entry
point information being used to initialise a secure context. It is the caller's
responsibility to check if S-EL2 is available on the system before requesting
this EL through the entry point information.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1

Merge changes from topic "bs/libc" into integration ...

* changes:
  libc: Consolidate the size_t and NULL definitions
  libc: Consolidate unified definitions
  libc: Unify intmax_t and uintmax_t on AArch32/64

libc: Consolidate the size_t and NULL definitions ...

Consolidate the definition of size_t to one header per AArch, and
the definition of NULL to one header

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82

libc: Consolidate unified definitions ...

As supporting architectures aside from AArch32 and AArch64 is not a
concern, keeping identical definitions in two places for a large part
of the libc seems counterproductive

The int128 types were left un-unified as __int128 is not supported by
gcc on AArch32

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf

libc: Unify intmax_t and uintmax_t on AArch32/64 ...

Conceptually, these are supposed to be the largest integers
representable in C, but GCC and Clang define them as long long for
compatibility.

Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: I7c0117f3be167342814d260a371889120dcf6576

Merge changes from topic "allwinner_bl31_size" into integration ...

* changes:
  Reduce space lost to object alignment
  imx: Fix multiple definition of ipc_handle
  imx: Fix missing inclusion of cdefs.h