2020-03-23 |
allwinner: H6: Fix GPIO and CCU memory map addresses
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The base address for both the GPIO and the clock unit of the H6 memory map
have been typo-ed. Fix them to match the Linux DT and the manual.
The H6 code use neither of them, so this doesn't change or fix anything
in the real world, but should be corrected anyway.
The issue was found and reported by Github user "armlabs".
Change-Id: Ic6fdfb732ce1cfc54cbb927718035624a06a9e08
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara
committed
on 23 Mar 2020
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2020-02-26 |
Merge "allwinner: Implement PSCI system suspend using SCPI" into integration
Olivier Deprez
authored
on 26 Feb 2020
TrustedFirmware Code Review
committed
on 26 Feb 2020
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Merge "allwinner: Add a msgbox driver for use with SCPI" into integration
Olivier Deprez
authored
on 26 Feb 2020
TrustedFirmware Code Review
committed
on 26 Feb 2020
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Merge "allwinner: Reserve and map space for the SCP firmware" into integration
Olivier Deprez
authored
on 26 Feb 2020
TrustedFirmware Code Review
committed
on 26 Feb 2020
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2020-02-25 |
Merge changes from topic "console_t_cleanup" into integration
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* changes:
marvell: Consolidate console register calls
uniphier: Use generic console_t data structure
spe: Use generic console_t data structure
LS 16550: Use generic console_t data structure
stm32: Use generic console_t data structure
rcar: Use generic console_t data structure
a3700: Use generic console_t data structure
16550: Use generic console_t data structure
imx: Use generic console_t data structure
Mark Dykes
authored
on 25 Feb 2020
TrustedFirmware Code Review
committed
on 25 Feb 2020
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16550: Use generic console_t data structure
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Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara
committed
on 25 Feb 2020
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2020-02-12 |
allwinner: Implement PSCI system suspend using SCPI
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If an SCP firmware is present and able to communicate via SCPI, then use
that to implement CPU and system power state transitions, including CPU
hotplug and system suspend. Otherwise, fall back to the existing CPU
power control implementation.
The last 16 KiB of SRAM A2 are reserved for the SCP firmware, and the
SCPI shared memory is at the very end of this region (and therefore the
end of SRAM A2). BL31 continues to start at the beginning of SRAM A2
(not counting the ARISC exception vector area) and fills up to the
beginning of the SCP firmware.
Because the SCP firmware is not loaded adjacent to the ARISC exception
vector area, the jump instructions used for exception handling cannot be
included in the SCP firmware image, and must be initialized here before
turning on the SCP.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I37b9b9636f94d4125230423726f3ac5e9cdb551c
Samuel Holland
committed
on 12 Feb 2020
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allwinner: Add a msgbox driver for use with SCPI
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The function names follow the naming convention used by the existing
ARM SCPI client.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I543bae7d46e206eb405dbedfcf7aeba88a12ca48
Samuel Holland
committed
on 12 Feb 2020
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allwinner: Reserve and map space for the SCP firmware
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The SCP firmware is allocated the last 16KiB of SRAM A2. This includes
the SCPI shared memory area, which must be mapped as MT_DEVICE to
prevent problems with cache coherency between the AP CPUs and the SCP.
For simplicity, map the whole SCP region as MT_DEVICE.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie39eb5ff281b8898a3c1d9748dc08755f528e2f8
Samuel Holland
committed
on 12 Feb 2020
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allwinner: Adjust SRAM A2 base to include the ARISC vectors
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The ARISC vector area consists of 0x4000 bytes before the beginning of
usable SRAM. Still, it is technically a part of SRAM A2, so include it
in the memory definition. This avoids the confusing practice of
subtracting from the beginning of the SRAM region when referencing the
ARISC vectors.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iae89e01aeab93560159562692e03e88306e2a1bf
Samuel Holland
committed
on 12 Feb 2020
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2020-01-24 |
allwinner: Unify Platform specific defines for PSCI module
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PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7aea86891e54522c88af5ff16795a575f9a9322d
Deepika Bhavnani
authored
on 13 Dec 2019
Soby Mathew
committed
on 24 Jan 2020
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2020-01-20 |
allwinner: Clean up MMU setup
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Remove the general BL31 mmap region: it duplicates the existing static
mapping for the entire SRAM region. Use the helper definitions when
applicable to simplify the code and add the MT_EXECUTE_NEVER flag.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I7a6b79e50e4b5c698774229530dd3d2a89e94a6d
Samuel Holland
authored
on 27 Oct 2019
Manish Pandey
committed
on 20 Jan 2020
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2020-01-15 |
allwinner: Reenable USE_COHERENT_MEM
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Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies the code, this is a beneficial change for
loaded image (.text) size, where we are still close to the size limit.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
Samuel Holland
authored
on 27 Oct 2019
Olivier Deprez
committed
on 15 Jan 2020
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2020-01-14 |
Merge "allwinner: Move the NOBITS region to SRAM A1" into integration
Alexei Fedorov
authored
on 14 Jan 2020
TrustedFirmware Code Review
committed
on 14 Jan 2020
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2019-12-29 |
allwinner: Remove unused include path
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Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95
Samuel Holland
committed
on 29 Dec 2019
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allwinner: Move the NOBITS region to SRAM A1
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This frees up space in SRAM A2 that will be used by the SCP firmware and
SCPI shared memory.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I8ce035257451e2d142666fe0cd045e59d4d57b35
Samuel Holland
committed
on 29 Dec 2019
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2019-12-13 |
allwinner: h6: power: Switch to using the AXP driver
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Chip ID checking and poweroff work just like they did before.
Regulators are now enabled just like on A64/H5.
This changes the signatures of the low-level register read/write
functions to match the interface expected by the common driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I14d63d171a094fa1375904928270fa3e21761646
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Convert AXP803 regulator setup code into a driver
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Previously, the A64/H5 and H6 platforms' PMIC setup code was entirely
independent. However, some H6 boards also need early regulator setup.
Most of the register interface and all of the device tree traversal code
can be reused between the AXP803 and AXP805. The main difference is the
hardware bus interface, so that part is left to the platforms. The
remainder is moved into a driver.
I factored out the bits that were obviously specific to the AXP803;
additional changes for compatibility with other PMICs can be made as
needed.
The only functional change is that rsb_init() now checks the PMIC's chip
ID register against the expected value. This was already being done in
the H6 version of the code.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icdcf9edd6565f78cccc503922405129ac27e08a2
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Use fdt_for_each_subnode
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This simplifies the code a bit. Verified to produce the same binary.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ie1ec1ce2ea39c46525840906826c90a8a7eff287
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Remove obsolete register check
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As of a561e41bf1d2 ("allwinner: power: add enable switches for DCDC1/5")
there are no longer regulators without an enable register provided.
Since it seems reasonable that this will continue to be the case, drop
the check.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Icd7ec26fc6450d053e6e6d855fc16229b1d65a39
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Remove duplicate DT check
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should_enable_regulator() is already checked in the regulators subnode
loop before setup_regulator() is called, so there's no need to check it
again here.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idb8b8a6e435246f4fb226bc84813449d80a0a977
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Build PMIC bus drivers only in BL31
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These are used by the PMIC setup code, which runs during BL31
initialization, and the PSCI shutdown code, also a part of BL31.
They can't be needed before BL31, or it wouldn't be possible to boot.
Allwinner platforms don't generally build anything but BL31 anyway, but
this change improves clarity and consistency with allwinner-common.mk.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I24f1d9ca8b4256e44badf5218d04d8690082babf
Samuel Holland
committed
on 13 Dec 2019
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allwinner: a64: power: Make sunxi_turn_off_soc static
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The function is only used in this file, and it doesn't make sense for it
to be used anywhere else.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iab18f082911edcdbc37ceeaff8c512be68e0cb0f
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Merge duplicate code in sunxi_power_down
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The action of last resort isn't going to change between SoCs. This moves
that code back to the PSCI implementation, where it more obviously
matches the code in sunxi_system_reset().
The two error messages say essentially the same thing anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I62ac35fdb5ed78a016e9b18281416f1dcea38a4a
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Clean up PMIC-related error handling
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- Check the return value from sunxi_init_platform_r_twi().
- Print the PMIC banner before doing anything that might fail.
- Remove double prefixes in error messages.
- Consistently omit the trailing period.
- No need to print the unknown SoC's ID, since we already did that
earlier in bl31_platform_setup().
- On the other hand, do print the ID of the unknown PMIC.
- Try to keep the messages concise, as the large string size in these
files was causing the firmware to spill into the next page.
- Downgrade the banner from NOTICE to INFO. It's purely informational,
and people should be using debug builds on untested hardware anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib909408a5fdaebe05470fbce48d245dd0bf040eb
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Synchronize PMIC enumerations
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Ensure that the default (zero) value represents the case where we take
no action. Previously, if a PLAT=sun50i_a64 build was booted on an
unknown SoC ID, it would be treated as an H5 at shutdown.
This removes some duplicate code and fixes error propagation on H6.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I4e51d8a43a56eccb0d8088593cb9908e52e782bc
Samuel Holland
committed
on 13 Dec 2019
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allwinner: Enable clock before resetting I2C/RSB
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The clock must be running for the module to be reset.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a
Samuel Holland
committed
on 13 Dec 2019
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Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration
Soby Mathew
authored
on 13 Dec 2019
TrustedFirmware Code Review
committed
on 13 Dec 2019
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2019-12-04 |
allwinner: Fix incorrect ARISC code patch offset check
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The current range check for the offset is wrong: it is counting bytes,
while indexing an array of uint32_t. Since the offset is always zero,
the parameter is unnecessary. Instead of adding more code to fix the
check, remove the parameter to avoid the problem entirely.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6
Samuel Holland
committed
on 4 Dec 2019
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2019-11-26 |
allwinner: power: Add DLDO4 power rail
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A64-OLinuXino family boards (maybe others too) uses PG for USB vbus
enable/disable. However PG is supplied by DLDO4, which is not present
in the list of known regulators. This patch adds DLD04 to it.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Change-Id: I31d3bb3e0004ccf5b282d08b530ee44979da0466
Stefan Mavrodiev
committed
on 26 Nov 2019
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