2015-01-28 |
Merge pull request #248 from jcastillo-arm/jc/tf-issues/212_1
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Allow BL3-2 to be loaded into the secure region of DRAM
danh-arm
committed
on 28 Jan 2015
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2015-01-26 |
Call reset handlers upon BL3-1 entry.
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This patch adds support to call the reset_handler() function in BL3-1 in the
cold and warm boot paths when another Boot ROM reset_handler() has already run.
This means the BL1 and BL3-1 versions of the CPU and platform specific reset
handlers may execute different code to each other. This enables a developer to
perform additional actions or undo actions already performed during the first
call of the reset handlers e.g. apply additional errata workarounds.
Typically, the reset handler will be first called from the BL1 Boot ROM. Any
additional functionality can be added to the reset handler when it is called
from BL3-1 resident in RW memory. The constant FIRST_RESET_HANDLER_CALL is used
to identify whether this is the first version of the reset handler code to be
executed or an overridden version of the code.
The Cortex-A57 errata workarounds are applied only if they have not already been
applied.
Fixes ARM-software/tf-issue#275
Change-Id: Id295f106e4fda23d6736debdade2ac7f2a9a9053
Yatharth Kochar
authored
on 20 Nov 2014
Achin Gupta
committed
on 26 Jan 2015
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FVP: Allow BL3-2 to sit in the secure region of DRAM
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This patch allows the secure payload (BL3-2) to be loaded in the
DRAM region secured by the TrustZone controller (top 16 MB of DRAM1).
The location of BL3-2 can be selected at build time by setting the
build flag FVP_TSP_RAM_LOCATION to one of the following options:
- 'tsram' : Trusted SRAM (this is the default option)
- 'tdram' : Trusted DRAM
- 'dram' : Secure region in DRAM1 (top 16MB configured by the
TrustZone controller)
The number of MMU tables in BL3-2 depends on its location in
memory: 3 in case it is loaded in DRAM, 2 otherwise.
Documentation updated accordingly.
Fixes ARM-software/tf-issues#212
Change-Id: I371eef3a4159f06a0c9e3c6c1f4c905b2f93803a
Juan Castillo
committed
on 26 Jan 2015
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2015-01-23 |
Validate power_state and entrypoint when executing PSCI calls
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This patch allows the platform to validate the power_state and
entrypoint information from the normal world early on in PSCI
calls so that we can return the error safely. New optional
pm_ops hooks `validate_power_state` and `validate_ns_entrypoint`
are introduced to do this.
As a result of these changes, all the other pm_ops handlers except
the PSCI_ON handler are expected to be successful. Also, the PSCI
implementation will now assert if a PSCI API is invoked without the
corresponding pm_ops handler being registered by the platform.
NOTE : PLATFORM PORTS WILL BREAK ON MERGE OF THIS COMMIT. The
pm hooks have 2 additional optional callbacks and the return type
of the other hooks have changed.
Fixes ARM-Software/tf-issues#229
Change-Id: I036bc0cff2349187c7b8b687b9ee0620aa7e24dc
Soby Mathew
committed
on 23 Jan 2015
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Remove `ns_entrypoint` and `mpidr` from parameters in pm_ops
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This patch removes the non-secure entry point information being passed
to the platform pm_ops which is not needed. Also, it removes the `mpidr`
parameter for platform pm hooks which are meant to do power management
operations only on the current cpu.
NOTE: PLATFORM PORTS MUST BE UPDATED AFTER MERGING THIS COMMIT.
Change-Id: If632376a990b7f3b355f910e78771884bf6b12e7
Soby Mathew
committed
on 23 Jan 2015
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2015-01-22 |
Remove coherent memory from the BL memory maps
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This patch extends the build option `USE_COHERENT_MEMORY` to
conditionally remove coherent memory from the memory maps of
all boot loader stages. The patch also adds necessary
documentation for coherent memory removal in firmware-design,
porting and user guides.
Fixes ARM-Software/tf-issues#106
Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
Soby Mathew
authored
on 8 Jan 2015
Dan Handley
committed
on 22 Jan 2015
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Move bakery algorithm implementation out of coherent memory
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This patch moves the bakery locks out of coherent memory to normal memory.
This implies that the lock information needs to be placed on a separate cache
line for each cpu. Hence the bakery_lock_info_t structure is allocated in the
per-cpu data so as to minimize memory wastage. A similar platform per-cpu
data is introduced for the platform locks.
As a result of the above changes, the bakery lock api is completely changed.
Earlier, a reference to the lock structure was passed to the lock implementation.
Now a unique-id (essentially an index into the per-cpu data array) and an offset
into the per-cpu data for bakery_info_t needs to be passed to the lock
implementation.
Change-Id: I1e76216277448713c6c98b4c2de4fb54198b39e0
Soby Mathew
authored
on 8 Jan 2015
Dan Handley
committed
on 22 Jan 2015
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2015-01-21 |
FVP: map non-secure DRAM1 in the MMU
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This patch maps the non-secure region of DRAM1 in the MMU. The
non-secure region comprises the whole DRAM1 (0x80000000 -
0xffffffff) excluding the top 16 MB (0xff000000 - 0xffffffff).
The TrustZone controller configures this 16 MB region as secure
memory, so it can not be accessed in non-secure mode.
The number of MMU tables in BL2 has been increased to 3 because
the new size of the non-secure region in DRAM requires an extra L2
table.
Change-Id: I5ad080c6e181f6b6060e15cebb1d18b7fa128cf5
Juan Castillo
committed
on 21 Jan 2015
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2015-01-16 |
Merge pull request #233 from jcastillo-arm/jc/tf-issues/254
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Juno: Add support for image overlaying in Trusted SRAM
danh-arm
committed
on 16 Jan 2015
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2015-01-12 |
Juno: Add support for image overlaying in Trusted SRAM
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This patch allows the BL3-1 NOBITS section to overlap the BL1 R/W
section since the former will always be used after the latter.
Similarly, the BL3-2 NOBITS section can overlay the BL2 image
when BL3-2 is loaded in Trusted SRAM.
Due to the current size of the images, there is no actual overlap.
Nevertheless, this reorganization may help to optimise the Trusted
SRAM usage when the images size grows.
Note that because BL3-1 NOBITS section is allowed to overlap the
BL1 R/W section, BL1 global variables will remain valid only until
execution reaches the BL3-1 entry point during a cold boot.
Documentation updated accordingly.
Fixes ARM-software/tf-issues#254
Change-Id: Id538f4d1c7f1f7858108280fd7b97e138572b879
Juan Castillo
committed
on 12 Jan 2015
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2014-12-10 |
Remove IRQ_SEC_SGI_8 constant
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In both FVP and Juno ports, IRQ #16, which is a PPI, is incorrectly
identified as secure SGI #8 through the constant IRQ_SEC_SGI_8.
This patch removes it.
Fixes ARM-software/tf-issues#282
Change-Id: I9e52d849611ffcd2b1f28e56dd156c5b217ed63e
Sandrine Bailleux
committed
on 10 Dec 2014
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2014-11-11 |
Merge pull request #220 from soby-mathew/sm/reassign_crash_console
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Use the BL3-1 runtime console as the crash console.
danh-arm
committed
on 11 Nov 2014
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2014-11-04 |
Use the BL3-1 runtime console as the crash console.
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This patch reassigns the crash console on Juno and FVP to use the runtime
BL3-1 console. The crash console is changed to SoC UART0 (UART2) from the
previous FPGA UART0 (UART0) on Juno. In FVP, it is changed from UART0 to
UART1.
Fixes ARM-software/tf-issues#256
Change-Id: I7df54f86ca00ec2652c27261dd66a94c12610816
Soby Mathew
committed
on 4 Nov 2014
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Merge pull request #219 from jcastillo-arm/jc/tf-issues/253
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Improvements to ARM GIC driver
Juno: Use the generic ARM GIC driver
danh-arm
committed
on 4 Nov 2014
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2014-10-31 |
Juno: Use the generic ARM GIC driver
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This patch replaces the usage of the GIC private driver in Juno with
the generic ARM GIC driver. The private driver is no longer necessary
and has been removed from the Juno port.
Fixes ARM-software/tf-issues#253
Change-Id: I6aaabc252e5e6fb5fcf44ab6d0febd9b38791056
Juan Castillo
committed
on 31 Oct 2014
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2014-10-29 |
Optimize Cortex-A57 cluster power down sequence on Juno
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This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.
This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.
Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
Soby Mathew
committed
on 29 Oct 2014
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2014-10-28 |
Merge pull request #217 from jcastillo-arm/jc/tf-issues/257
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FVP: keep shared data in Trusted SRAM
danh-arm
committed
on 28 Oct 2014
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Merge pull request #216 from vikramkanigiri/vk/juno_standby_support
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Juno: Support entry into a standby state
danh-arm
committed
on 28 Oct 2014
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2014-10-22 |
FVP: keep shared data in Trusted SRAM
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This patch deprecates the build option to relocate the shared data
into Trusted DRAM in FVP. After this change, shared data is always
located at the base of Trusted SRAM. This reduces the complexity
of the memory map and the number of combinations in the build
options.
Fixes ARM-software/tf-issues#257
Change-Id: I68426472567b9d8c6d22d8884cb816f6b61bcbd3
Juan Castillo
committed
on 22 Oct 2014
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2014-10-21 |
Juno: Support entry into a standby state
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This patch adds support on the Juno platform for entering a wfi in
response to a PSCI CPU_SUSPEND call where the state type is a
standby state.
Change-Id: I0a102dee1f8d2ad936c63ad1d1d3ad001a4a4768
Vikram Kanigiri
committed
on 21 Oct 2014
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2014-10-14 |
Juno: Reserve some DDR-DRAM for secure use
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This patch configures the TrustZone Controller in Juno to split
the 2GB DDR-DRAM memory at 0x80000000 into Secure and Non-Secure
regions:
- Secure DDR-DRAM: top 16 MB, except for the last 2 MB which are
used by the SCP for DDR retraining
- Non-Secure DDR-DRAM: remaining DRAM starting at base address
Build option PLAT_TSP_LOCATION selects the location of the secure
payload (BL3-2):
- 'tsram' : Trusted SRAM (default option)
- 'dram' : Secure region in the DDR-DRAM (set by the TrustZone
controller)
The MMU memory map has been updated to give BL2 permission to load
BL3-2 into the DDR-DRAM secure region.
Fixes ARM-software/tf-issues#233
Change-Id: I6843fc32ef90aadd3ea6ac4c7f314f8ecbd5d07b
Juan Castillo
committed
on 14 Oct 2014
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2014-10-09 |
Juno: Use TZC-400 driver calls
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This patch replaces direct accesses to the TZC-400 registers by the
appropiate calls to the generic driver available in the Trusted
Firmware in order to initialize the TrustZone Controller.
Functions related to the initialization of the secure memory,
like the TZC-400 configuration, have been moved to a new file
'plat_security.c'. This reorganization makes easier to set up
the secure memory from any BL stage.
TZC-400 initialization has been moved from BL1 to BL2 because BL1
does not access the non-secure memory. It is BL2's responsibility
to enable and configure the TZC-400 before loading the next BL
images.
In Juno, BL3-0 initializes some of the platform peripherals, like
the DDR controller. Thus, BL3-0 must be loaded before configuring
the TrustZone Controller. As a consequence, the IO layer
initialization has been moved to early platform initialization.
Fixes ARM-software/tf-issues#234
Change-Id: I83dde778f937ac8d2996f7377e871a2e77d9490e
Juan Castillo
committed
on 9 Oct 2014
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2014-09-25 |
Merge pull request #214 from soby-mathew/sm/bl_specific_mmap
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Create BL stage specific translation tables
achingupta
committed
on 25 Sep 2014
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Create BL stage specific translation tables
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This patch uses the IMAGE_BL<x> constants to create translation tables specific
to a boot loader stage. This allows each stage to create mappings only for areas
in the memory map that it needs.
Fixes ARM-software/tf-issues#209
Change-Id: Ie4861407ddf9317f0fb890fc7575eaa88d0de51c
Soby Mathew
authored
on 3 Sep 2014
Achin Gupta
committed
on 25 Sep 2014
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2014-09-22 |
Remove BSS section access by 'plat_print_gic' during crash reporting
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This patch avoids the problem of crash reporting mechanism accessing
global data in BSS by 'plat_print_gic_regs' for FVP platforms. Earlier
it depended on the global 'plat_config' object for the GIC Base address
in FVP platforms which would have caused exception if it were accessed
before the BSS was initialized. It is now fixed by dynamically
querying the V2M_SYS_ID to find the FVP model type and accordingly
selecting the appropriate GIC Base address.
This patch also fixes the 'plat_print_gic_regs' to use the correct GIC
Distributor base address for printing GICD_IS_PENDR register values
for both Juno and FVP platforms.
Fixes ARM-Software/tf-issues#236
Change-Id: I545c7b908b3111419bf27db0575ce86acf86784b
Soby Mathew
committed
on 22 Sep 2014
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2014-08-27 |
Miscellaneous documentation fixes
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This patch gathers miscellaneous minor fixes to the documentation, and comments
in the source code.
Change-Id: I631e3dda5abafa2d90f464edaee069a1e58b751b
Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
Co-Authored-By: Dan Handley <dan.handley@arm.com>
Sandrine Bailleux
authored
on 6 Aug 2014
Dan Handley
committed
on 27 Aug 2014
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2014-08-21 |
Rationalize UART usage among different BL stages
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This patch changes the UART port assignment for various BL stages
so as to make it consistent on the platform ports. The BL1, BL2 and
BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port.
The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno
port.
This provides an interim fix to ARM-software/tf-issues#220 until
support is added for changing the UART port for a BL image between
cold boot and runtime.
Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a
Soby Mathew
committed
on 21 Aug 2014
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Juno: Read primary CPU MPID from SCC GPR_1
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This patch removes the PRIMARY_CPU definition hardcoded in the
Juno port. Instead, the primary CPU is obtained at runtime by
reading the SCC General Purpose Register 1 (GPR_1), whose value
is copied by the SCP into shared memory during the boot process.
Change-Id: I3981daa92eb7142250712274cf7f655b219837f5
Juan Castillo
authored
on 12 Aug 2014
Soby Mathew
committed
on 21 Aug 2014
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Juno: Implement PSCI SYSTEM_OFF and SYSTEM_RESET APIs
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This patch adds the Juno platform specific handlers for PSCI
SYSTEM_OFF and SYSTEM_RESET operations.
Change-Id: Ie389adead533ec2314af44d721b4d0f306147c7d
Juan Castillo
authored
on 12 Aug 2014
Soby Mathew
committed
on 21 Aug 2014
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Juno: Add support for Test Secure-EL1 Payload
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This patch implements the TSP on Juno. It executes from on-chip Trusted
SRAM.
Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.
This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest allocations
since they will most probably grow the most.
This patch also adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.
Change-Id: I1c5b51858700027ee283ac85d18e06863a27c72e
Sandrine Bailleux
authored
on 17 Jul 2014
Soby Mathew
committed
on 21 Aug 2014
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