Optimize Cortex-A57 cluster power down sequence on Juno
This patch optimizes the Cortex-A57 cluster power down sequence by not flushing the Level1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. This optimization can be enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build flag. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This patch also renames the cpu-errata-workarounds.md to cpu-specific-build-macros.md as this facilitates documentation of both CPU Specific errata and CPU Specific Optimization build macros. Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
WIP_v2.3-LS
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Makefile |
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docs/cpu-errata-workarounds.md 100644 → 0 |
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docs/cpu-specific-build-macros.md 0 → 100644 |
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docs/firmware-design.md |
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lib/cpus/aarch64/cortex_a57.S |
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lib/cpus/cpu-errata.mk 100644 → 0 |
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lib/cpus/cpu-ops.mk 0 → 100644 |
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plat/juno/platform.mk |
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