Merge "rcar_gen3: drivers: ddr: Move DDR drivers out of staging" into integration

Merge "Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain"" into integration

Merge "smccc: add get smc function id num macro" into integration

Merge "Simplify PMF helper macro definitions across header files" into integration

Merge "Remove redundant declarations." into integration

Merge "Tegra194: mce: fix error code signedness" into integration

smccc: add get smc function id num macro ...

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2953f0a6f35bc678402bc185640d1f328b065af5

Simplify PMF helper macro definitions across header files ...

In further patches, we aim to enable -Wredundant-decls by default.
This rearragement of helper macros is necessary to make Coverity
tool happy as well as making sure there are no redundant function
declarations for PMF related declarations.

Also, PMF related macros were added to provide appropriate function
declarations for helper APIs which capture PSCI statistics.

Change-Id: I36273032dde8fa079ef71235ed3a4629c5bfd981
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Remove redundant declarations. ...

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain" ...

This reverts commit de9bf1d.

Change-Id: Iebb6297ce290a10ee850bf6a9c71e7eb530b085f

Tegra194: mce: fix error code signedness ...

The MCE driver's helper functions were using postive values as error
codes.

This patch updates the functions to return negative values as error
codes instead. Some functions are updated to use the right error code.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6

Merge "A5DS: Change boot address to point to DDR address" into integration

Merge "A5DS: Correct system freq, Cache Writeback Granule" into integration

A5DS: Change boot address to point to DDR address ...

Point boot address to DDR location for booting A5DS FPGA
FIP, Kernel and rootfs are sideloaded to DDR
Also move BL2 to higher address in DDR

Change-Id: Ia2a57a0bda776a1a0a96bcd3cfb5c6cd2cf4dc04
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

A5DS: Correct system freq, Cache Writeback Granule ...

Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeback

Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

Merge "GCC: Upgrade to version 9.2-2019.12 of toolchain" into integration

rcar_gen3: drivers: ddr: Move DDR drivers out of staging ...

Now that DDR drivers are mostly cleaned up , move them out of staging.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9de63f847a0ef9ac27a79fb0f848c351fd7f4da6

Merge "drivers: add a driver for snoop control unit" into integration

drivers: add a driver for snoop control unit ...

The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.

The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
  processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
  L2 accesses
- manage ACP accesses.

Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.

This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT

Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

GCC: Upgrade to version 9.2-2019.12 of toolchain ...

This toolchain provides multiple cross compilers and are publicly
available on www.developer.arm.com

We thoroughly test TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I2360a3ac6705c68dca781b85e9894867df255b3e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "bl31: Split into two separate memory regions" into integration

Merge "mediatek: mt8183: add Vmodem/Vcore DVS init level" into integration

Merge "allwinner: Remove unused include path" into integration

Merge "rockchip: rk3328: Enable workaround for erratum 855873" into integration

Merge "Workaround for Hercules erratum 1688305" into integration

Merge "uniphier: run BL33 at EL2" into integration

allwinner: Remove unused include path ...

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ia2f69e26e34462e113bc2cad4dcb923e20b8fb95

bl31: Split into two separate memory regions ...

Some platforms are extremely memory constrained and must split BL31
between multiple non-contiguous areas in SRAM. Allow the NOBITS
sections (.bss, stacks, page tables, and coherent memory) to be placed
in a separate region of RAM from the loaded firmware image.

Because the NOBITS region may be at a lower address than the rest of
BL31, __RW_{START,END}__ and __BL31_{START,END}__ cannot include this
region, or el3_entrypoint_common would attempt to invalidate the dcache
for the entire address space. New symbols __NOBITS_{START,END}__ are
added when SEPARATE_NOBITS_REGION is enabled, and the dcached for the
NOBITS region is invalidated separately.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Idedfec5e4dbee77e94f2fdd356e6ae6f4dc79d37

uniphier: run BL33 at EL2 ...

All the SoCs in 64-bit UniPhier SoC family support EL2.

Just hard-code MODE_EL2 instead of using el_implemented() helper.

Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

mediatek: mt8183: add Vmodem/Vcore DVS init level ...

spm resume will restore Vmodem/Vcore voltages
back based on the SPM_DVS_LEVEL.

Change-Id: I37ff7ce4ba62219c1858acea816c5bc9ce6c493e
Signed-off-by: Roger Lu <roger.lu@mediatek.com>