2014-05-20 |
fvp: Move TSP from Secure DRAM to Secure SRAM
...
The TSP used to execute from secure DRAM on the FVPs because there was
not enough space in Trusted SRAM to fit it in. Thanks to recent RAM
usage enhancements being implemented, we have made enough savings for
the TSP to execute in SRAM.
However, there is no contiguous free chunk of SRAM big enough to hold
the TSP. Therefore, the different bootloader images need to be moved
around to reduce memory fragmentation. This patch keeps the overall
memory layout (i.e. keeping BL1 R/W at the bottom, BL2 at the top and
BL3-1 in between) but moves the base addresses of all the bootloader
images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest slice
of the cake since they will most probably grow the most.
A few useful numbers for reference (valid at the time of this patch):
|-----------------------|-------------------------------
| image size (debug) | extra space for the future
--------|-----------------------|-------------------------------
BL1 R/W | 20 KB | 4 KB
BL2 | 44 KB | 4 KB
BL3-1 | 108 KB | 12 KB
BL3-2 | 56 KB | 8 KB
--------|-----------------------|-------------------------------
Total | 228 KB | 28 KB = 256 KB
--------|-----------------------|-------------------------------
Although on FVPs the TSP now executes from Trusted SRAM by default,
this patch keeps the option to execute it from Trusted DRAM. This is
controlled by the build configuration 'TSP_RAM_LOCATION'.
Fixes ARM-Software/tf-issues#81
Change-Id: Ifb9ef2befa9a2d5ac0813f7f79834df7af992b94
Sandrine Bailleux
committed
on 20 May 2014
|
TSP: Let the platform decide which secure memory to use
...
The TSP's linker script used to assume that the TSP would
execute from secure DRAM. Although it is currently the case
on FVPs, platforms are free to use any secure memory they wish.
This patch introduces the flexibility to load the TSP into any
secure memory. The platform code gets to specify the extents of
this memory in the platform header file, as well as the BL3-2 image
limit address. The latter definition allows to check in a generic way
that the BL3-2 image fits in its bounds.
Change-Id: I9450f2d8b32d74bd00b6ce57a0a1542716ab449c
Sandrine Bailleux
committed
on 20 May 2014
|
2014-05-16 |
Add build configuration for timer save/restore
...
At present, non-secure timer register contents are saved and restored as
part of world switch by BL3-1. This effectively means that the
non-secure timer stops, and non-secure timer interrupts are prevented
from asserting until BL3-1 switches back, introducing latency for
non-secure services. Often, secure world might depend on alternate
sources for secure interrupts (secure timer or platform timer) instead
of non-secure timers, in which case this save and restore is
unnecessary.
This patch introduces a boolean build-time configuration NS_TIMER_SWITCH
to choose whether or not to save and restore non-secure timer registers
upon world switch. The default choice is made not to save and restore
them.
Fixes ARM-software/tf-issues#148
Change-Id: I1b9d623606acb9797c3e0b02fb5ec7c0a414f37e
Jeenu Viswambharan
committed
on 16 May 2014
|
Document summary of build options in user guide
...
Change-Id: I6bd077955bf3780168a874705974bbe72ea0f5f1
Jeenu Viswambharan
committed
on 16 May 2014
|
Reorganize build options
...
At present, various build options are initialized at various places in
the Makefile. This patch gathers all build option declarations at the
top of the Makefile and assigns them default values.
Change-Id: I9f527bc8843bf69c00cb754dc60377bdb407a951
Jeenu Viswambharan
committed
on 16 May 2014
|
Introduce convenience functions to build
...
This patch introduces two convenience functions to the build system:
- assert_boolean: asserts that a given option is assigned either 0 or
1 as values
- add_define: helps add/append macro definitions to build tool command
line. This also introduces the variable DEFINES which is used to
collect and pass all relevant configurations to build tools
Change-Id: I3126894b034470d39858ebb3bd183bda681c7126
Jeenu Viswambharan
committed
on 16 May 2014
|
Merge pull request #71 from sandrine-bailleux:sb/fix-tsp-fvp-makefile
Andrew Thoelke
committed
on 16 May 2014
|
Merge pull request #69 from sandrine-bailleux:sb/split-mmu-fcts-per-el
Andrew Thoelke
committed
on 16 May 2014
|
Merge pull request #68 from jcastillo-arm/jc/tf-issues/137
...
Change-Id: If8744c38c2d5c50caa7454b055e2ba418cf1e8bf
Andrew Thoelke
committed
on 16 May 2014
|
Merge pull request #66 from athoelke/tzc-config-fix
...
Fixes for TZC configuration on FVP
danh-arm
committed
on 16 May 2014
|
2014-05-13 |
fvp: Use the right implem. of plat_report_exception() in BL3-2
...
On FVP, the file 'plat/fvp/aarch64/plat_helpers.S' contains an
FVP-specific implementation of the function 'plat_report_exception()',
which is meant to override the default implementation. However, this
file was not included into the BL3-2 image, meaning it was still
using the default implementation. This patch fixes the FVP makefile
to compile this file in.
Change-Id: I3d44b9ec3a9de7e2762e0887d3599b185d3e28d2
Sandrine Bailleux
committed
on 13 May 2014
|
Fix C accessors to GIC distributor registers with set/clear semantics
...
This patch fixes C accessors to GIC registers that follow a set/clear
semantic to change the state of an interrupt, instead of read/write/modify.
These registers are:
Set-Enable
Clear-Enable
Set-Pending
Clear-Pending
Set-Active
Clear-Active
For instance, to enable an interrupt we write a one to the corresponding bit
in the Set-Enable register, whereas to disable it we write a one to the
corresponding bit in the Clear-Enable register.
Fixes ARM-software/tf-issues#137
Change-Id: I3b66bad94d0b28e0fe08c9042bac0bf5ffa07944
Juan Castillo
committed
on 13 May 2014
|
2014-05-12 |
Fixes for TZC configuration on FVP
...
The TZC configuration on FVP was incorrectly allowing both secure
and non-secure accesses to the DRAM, which can cause aliasing
problems for software. It was also not enabling virtio access on
some models.
This patch fixes both of those issues. The patch also enabless
non-secure access to the DDR RAM for all devices with defined IDs.
The third region of DDR RAM has been removed from the configuration
as this is not used in any of the FVP models.
Fixes ARM-software/tf-issues#150
Fixes ARM-software/tf-issues#151
Change-Id: I60ad5daaf55e14f178affb8afd95d17e7537abd7
Andrew Thoelke
committed
on 12 May 2014
|
2014-05-09 |
fvp: Provide per-EL MMU setup functions
...
Instead of having a single version of the MMU setup functions for all
bootloader images that can execute either in EL3 or in EL1, provide
separate functions for EL1 and EL3. Each bootloader image can then
call the appropriate version of these functions. The aim is to reduce
the amount of code compiled in each BL image by embedding only what's
needed (e.g. BL1 to embed only EL3 variants).
Change-Id: Ib86831d5450cf778ae78c9c1f7553fe91274c2fa
Sandrine Bailleux
committed
on 9 May 2014
|
Introduce IS_IN_ELX() macros
...
The goal of these macros is to improve code readability by providing
a concise way to check whether we are running in the expected
exception level.
Change-Id: If9aebadfb6299a5196e9a582b442f0971d9909b1
Sandrine Bailleux
committed
on 9 May 2014
|
2014-05-08 |
Merge pull request #65 from vikramkanigiri/vk/console_init
...
Ensure a console is initialized before it is used
danh-arm
committed
on 8 May 2014
|
Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1
...
Preserve x19-x29 across world switch for exception handling
danh-arm
committed
on 8 May 2014
|
Ensure a console is initialized before it is used
...
This patch moves console_init() to bl32_early_platform_setup(). It
also ensures that console_init() is called in each
blX_early_platform_setup() function before the console is used
e.g. through a printf call in an assert() statement.
Fixes ARM-software/TF-issues#127
Change-Id: I5b1f17e0152bab674d807d2a95ff3689c5d4794e
Vikram Kanigiri
committed
on 8 May 2014
|
Merge pull request #62 from athoelke/set-little-endian-v2
...
Set processor endianness immediately after RESET v2
danh-arm
committed
on 8 May 2014
|
Preserve x19-x29 across world switch for exception handling
...
Previously exception handlers in BL3-1, X19-X29 were not saved
and restored on every SMC/trap into EL3. Instead these registers
were 'saved as needed' as a side effect of the A64 ABI used by the C
compiler.
That approach failed when world switching but was not visible
with the TSP/TSPD code because the TSP is 64-bit, did not
clobber these registers when running and did not support pre-emption
by normal world interrupts. These scenarios showed
that the values in these registers can be passed through a world
switch, which broke the normal and trusted world assumptions
about these registers being preserved.
The Ideal solution saves and restores these registers when a
world switch occurs - but that type of implementation is more complex.
So this patch always saves and restores these registers on entry and
exit of EL3.
Fixes ARM-software/tf-issues#141
Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
Soby Mathew
committed
on 8 May 2014
|
Merge pull request #58 from athoelke/optimise-cache-flush-v2
...
Optimise data cache clean/invalidate operation v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #61 from athoelke/use-mrs-msr-from-assembler-v2
...
Use MRS/MSR instructions in assembler code v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #60 from athoelke/disable-mmu-v2
...
Replace disable_mmu with assembler version v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #59 from athoelke/review-barriers-v2
...
Correct usage of data and instruction barriers v2
danh-arm
committed
on 8 May 2014
|
Merge pull request #57 from sandrine-bailleux/sb/remove-pl011-base
...
Remove unused 'PL011_BASE' macro
danh-arm
committed
on 8 May 2014
|
Remove unused 'PL011_BASE' macro
...
'PL011_BASE' macro is no longer used because the right UART base
address is now directly given to the 'console_init()' function.
This patch removes it.
Change-Id: I94759c99602df4876291a56f9f6a75de337a65ec
Sandrine Bailleux
committed
on 8 May 2014
|
2014-05-07 |
Optimise data cache clean/invalidate operation
...
The data cache clean and invalidate operations dcsw_op_all()
and dcsw_op_loius() were implemented to invoke a DSB and ISB
barrier for every set/way operation. This adds a substantial
performance penalty to an already expensive operation.
These functions have been reworked to provide an optimised
implementation derived from the code in section D3.4 of the
ARMv8 ARM. The helper macro setup_dcsw_op_args has been moved
and reworked alongside the implementation.
Fixes ARM-software/tf-issues#146
Change-Id: Icd5df57816a83f0a842fce935320a369f7465c7f
Andrew Thoelke
committed
on 7 May 2014
|
Remove unused or invalid asm helper functions
...
There are a small number of non-EL specific helper functions
which are no longer used, and also some unusable helper
functions for non-existant registers.
This change removes all of these functions.
Change-Id: Idd656cef3b59cf5c46fe2be4029d72288b649c24
Andrew Thoelke
committed
on 7 May 2014
|
Access system registers directly in assembler
...
Instead of using the system register helper functions to read
or write system registers, assembler coded functions should
use MRS/MSR instructions. This results in faster and more
compact code.
This change replaces all usage of the helper functions with
direct register accesses.
Change-Id: I791d5f11f257010bb3e6a72c6c5ab8779f1982b3
Andrew Thoelke
committed
on 7 May 2014
|
Replace disable_mmu with assembler version
...
disable_mmu() cannot work as a C function as there is no control
over data accesses generated by the compiler between disabling and
cleaning the data cache. This results in reading stale data from
main memory.
As assembler version is provided for EL3, and a variant that also
disables the instruction cache which is now used by the BL1
exception handling function.
Fixes ARM-software/tf-issues#147
Change-Id: I0cf394d2579a125a23c2f2989c2e92ace6ddb1a6
Andrew Thoelke
committed
on 7 May 2014
|