2019-05-22 |
doc: Use proper note and warning annotations
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The documentation contains plenty of notes and warnings. Enable
special rendering of these blocks by converting the note prefix
into a .. note:: annotation.
Change-Id: I34e26ca6bf313d335672ab6c2645741900338822
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 22 May 2019
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doc: Set correct syntax highlighting style
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Several code blocks do not specify a language for syntax
highlighting. This results in Sphinx using a default highlighter
which is Python.
This patch adds the correct language to each code block that doesn't
already specify it.
Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 22 May 2019
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doc: Remove per-page contents lists
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These are no longer needed as there will always be a table of contents
rendered to the left of every page.
Some of these lists can be quite long and, when opening a page, the
reader sees nothing but a huge list of contents! After this patch,
the document contents are front-and-centre and the contents are
nicely rendered in the sidebar without duplication.
Change-Id: I444754d548ec91d00f2b04e861de8dde8856aa62
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 22 May 2019
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doc: Reformat platform port documents
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The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:
1) Make sure each port has a proper name and title (incl. owner)
2) Correct use of headings, subheadings, etc in each port
3) Resolve any naming conflicts between documents
Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 22 May 2019
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2019-05-21 |
doc: Move documents into subdirectories
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This change creates the following directories under docs/
in order to provide a grouping for the content:
- components
- design
- getting_started
- perf
- process
In each of these directories an index.rst file is created
and this serves as an index / landing page for each of the
groups when the pages are compiled. Proper layout of the
top-level table of contents relies on this directory/index
structure.
Without this patch it is possible to build the documents
correctly with Sphinx but the output looks messy because
there is no overall hierarchy.
Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 21 May 2019
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2019-05-09 |
Initialize platform for MediaTek mt8183
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- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver
Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
kenny liang
committed
on 9 May 2019
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2019-04-29 |
Merge changes from topic "avenger96" into integration
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* changes:
fdts: Fix DTC warnings for STM32MP1 platform
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
stm32mp1: Add Avenger96 board support
Soby Mathew
authored
on 29 Apr 2019
TrustedFirmware Code Review
committed
on 29 Apr 2019
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2019-04-26 |
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
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Since STM32MP1 platform supports different boards, it is necessary
to build for a particular board. With the current instructions, the
user has to modify the DTB_FILE_NAME variable in platform.mk for
building for a particular board, but this can be avoided by passing
the appropriate board DTB name via DTB_FILE_NAME make variable.
Hence document the same in platform doc.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: I16797e7256c7eb699a7b8846356fe430d0fe0aa1
Manivannan Sadhasivam
committed
on 26 Apr 2019
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2019-04-25 |
rockchip: document platform
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This adds a rockchip.rst to docs/plat documenting the general
approach to using the Rockchip ATF platforms together with the
supported bootloaders and also adds myself as maintainer after
making sure Tony Xie is ok with that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Idce53d15eff4ac6de05bbb35d86e57ed50d0cbb9
Heiko Stuebner
committed
on 25 Apr 2019
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2019-04-23 |
stm32mp1: add OP-TEE support
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Support booting OP-TEE as BL32 boot stage and secure runtime
service.
OP-TEE executes in internal RAM and uses a secure DDR area to store
the pager pagestore. Memory mapping and TZC are configured accordingly
prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where
a header file describes the effective boot images. This change
post processes header file content to get OP-TEE load addresses
and set OP-TEE boot arguments.
Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Yann Gautier
committed
on 23 Apr 2019
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2019-04-02 |
plat: gxl: Add documentation on building GXL image
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Also adds a maintainer for GXL.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Remi Pommarel
committed
on 2 Apr 2019
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2019-03-12 |
plat: imx8m: Add the basic support for imx8mm
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The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is 14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators
this patch add the basic support for i.MX8MM.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Jacky Bai
committed
on 12 Mar 2019
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2019-03-01 |
Merge pull request #1751 from vwadekar/tegra-scatter-file-support
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Tegra scatter file support
Antonio Niño Díaz
authored
on 1 Mar 2019
GitHub
committed
on 1 Mar 2019
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2019-02-27 |
Tegra: Support for scatterfile for the BL31 image
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This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.
In order to enable the scatterfile usage the following changes
have been made:
* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
to compile BL31
* update pubsub.h to add sections to the scatterfile
NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.
Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 27 Feb 2019
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Merge pull request #1834 from thloh85-intel/s10_bl31
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plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
Antonio Niño Díaz
authored
on 27 Feb 2019
GitHub
committed
on 27 Feb 2019
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2019-02-25 |
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
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This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Tien Hock, Loh
committed
on 25 Feb 2019
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2019-02-22 |
Merge pull request #1836 from Yann-lms/docs_and_m4
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Update documentation for STM32MP1 and add Cortex-M4 support
Antonio Niño Díaz
authored
on 22 Feb 2019
GitHub
committed
on 22 Feb 2019
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2019-02-20 |
docs: stm32mp1: add links to documentation
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A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.
Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 20 Feb 2019
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2019-02-19 |
Documentation for Versatile Express Fixed Virtual Platforms
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This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.
Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c
Signed-off-by: Usama Arif <usama.arif@arm.com>
Usama Arif
committed
on 19 Feb 2019
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2019-02-08 |
doc: Fix broken external links
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Using Sphinx linkcheck on the TF-A docs revealed some broken
or permanently-redirected links. These have been updated where
possible.
Change-Id: Ie1fead47972ede3331973759b50ee466264bd2ee
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 8 Feb 2019
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2019-02-05 |
docs: add Tegra186 information to nvidia-tegra.rst
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This patch adds information about the Tegra186 platforms to the
docs.
Change-Id: I69525c60a0126030dc15505ec7f02ccf8250be6f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 5 Feb 2019
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2019-01-23 |
Merge pull request #1768 from bryanodonoghue/integration+linaro_warp7-tbb
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Integration+linaro warp7 tbb
Antonio Niño Díaz
authored
on 23 Jan 2019
GitHub
committed
on 23 Jan 2019
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2019-01-18 |
Tegra: lib: library for profiling the cold boot path
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The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.
This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.
Original change by Akshay Sharan <asharan@nvidia.com>
Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 18 Jan 2019
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docs: warp7: Update WaRP7 description for TBB
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This patch updates the WaRP7 build descriptions for booting WaRP7 in
Trusted Board Boot mode. TBB is the only mode we really intend to support
for this board so rather than maintain documentation for the old way of
doing it, this patch updates the description for TBB mode only.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Bryan O'Donoghue
committed
on 18 Jan 2019
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2019-01-16 |
Tegra: support to set the L2 ECC and Parity enable bit
...
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.
* with some coverity fix:
MISRA C-2012 Directive 4.6
MISRA C-2012 Rule 2.5
MISRA C-2012 Rule 10.3
MISRA C-2012 Rule 10.4
Change-Id: Id7303bbbdc290b52919356c31625847b8904b073
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Harvey Hsieh
authored
on 23 Nov 2016
Varun Wadekar
committed
on 16 Jan 2019
|
2018-12-04 |
plat: imx: Add i.MX8MQ basic support
...
i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consumer home audio to industrial building
automation and mobile computers
this patchset add the basic supoort to boot up
the 4 X A53. more feature will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Bai Ping
committed
on 4 Dec 2018
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2018-11-20 |
rpi3: fix bad formatting in rpi3.rst
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d4fd0219 (pull request #1685) introduced unwanted formatting
such as bold/italic in the description for RPI3_USE_UEFI_MAP.
Pete Batard
committed
on 20 Nov 2018
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2018-11-19 |
rpi3: add RPI3_USE_UEFI_MAP build option
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The default Raspberry Pi 3 memory mapping for ATF is geared towards
the use of uboot + Linux. This creates issues when trying to use
ATF with an UEFI payload and Windows on ARM64.
We therefore introduce new build option RPI3_USE_UEFI_MAP, that
enables the build process to use an alternate memory mapping that
is compatible with UEFI + Windows (as well as UEFI + Linux).
Fixes ARM-software/tf-issues#649
Signed-off-by: Pete Batard <pete@akeo.ie>
Pete Batard
committed
on 19 Nov 2018
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2018-11-13 |
rpi3: add RPI3_RUNTIME_UART build option
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Some OSes (e.g. Ubuntu 18.04 LTS on Raspberry Pi 3) may disable the
runtime UART in a manner that prevents the system from rebooting if
ATF tries to send runtime messages there.
Also, we don't want the firmware to share the UART with normal
world, as this can be a DoS attack vector into the secure world.
This patch fixes these 2 issues by introducing new build option
RPI3_RUNTIME_UART, that disables the runtime UART by default.
Fixes ARM-software/tf-issues#647
Signed-off-by: Pete Batard <pete@akeo.ie>
Pete Batard
committed
on 13 Nov 2018
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2018-11-09 |
arm64: versal: Add support for new Xilinx Versal ACAPs
...
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.
This patch adds Virtual QEMU platform support for
this SoC "versal_virt".
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu
committed
on 9 Nov 2018
|