2014-05-22 |
Split platform.h into separate headers
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Previously, platform.h contained many declarations and definitions
used for different purposes. This file has been split so that:
* Platform definitions used by common code that must be defined
by the platform are now in /plat/<PLAT>/platform_def.h.
* Platform definitions specific to the FVP platform are now in
/plat/fvp/fvp_def.h.
* Platform API declarations specific to the FVP platform are now
in /plat/fvp/fvp_private.h.
* The remaining platform API declarations that must be ported by
each platform are still in platform.h but this file has been
moved to /include/plat/common since this can be shared by all
platforms.
Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a
Dan Handley
authored
on 14 May 2014
Andrew Thoelke
committed
on 22 May 2014
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Remove unused data declarations
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Some data variables were declared but not used. These have been
removed.
Change-Id: I038632af3c32d88984cd25b886c43ff763269bf9
Dan Handley
authored
on 14 May 2014
Andrew Thoelke
committed
on 22 May 2014
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Remove extern keyword from function declarations
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Function declarations implicitly have external linkage so do not
need the extern keyword.
Change-Id: Ia0549786796d8bf5956487e8996450a0b3d79f32
Dan Handley
authored
on 14 May 2014
Andrew Thoelke
committed
on 22 May 2014
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Limit BL3-1 read/write access to SRAM
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At present BL3-1 has access to all of the SRAM, including
regions that are mapped as read-only and non-cacheable by other
firmware images.
This patch restricts BL3-1 to only be able to read/write from
memory used for its own data sections
Change-Id: I26cda1b9ba803d91a9eacda768f3ce7032c6db94
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #97 from athoelke:at/tsp-entrypoints
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Conflicts:
bl32/tsp/tsp_main.c
Change-Id: Ieae4532658dc782685bc6926c774a7c65201d954
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #84 from soby-mathew:sm/support_normal_irq_in_tsp
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #79 from achingupta:ag/tf-issues#104
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Conflicts:
plat/fvp/bl32_plat_setup.c
plat/fvp/platform.mk
services/spd/tspd/tspd_main.c
Change-Id: I43fbfb7e085c89f8c051ce15687365ba8324d02e
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #98 from jcastillo-arm:jc/tf-issues/149
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #87 from sandrine-bailleux:sb/tf-issue-81
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #95 from danh-arm:dh/tf-issues#68
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #96 from vikramkanigiri:vk/tf-issues-133
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #67 from achingupta:ag/psci_standby_bug_fix
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #91 from linmaonly/lin_dev
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Address issue 156: 64-bit addresses get truncated
Andrew Thoelke
committed
on 22 May 2014
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Reserve some DDR DRAM for secure use on FVP platforms
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TZC-400 is configured to set the last 16MB of DRAM1 as secure memory and
the rest of DRAM as non-secure. Non-secure software must not attempt to
access the 16MB secure area.
Device tree files (sources and binaries) have been updated to match this
configuration, removing that memory from the Linux physical memory map.
To use UEFI and Linux with this patch, the latest version of UEFI and
the updated device tree files are required. Check the user guide in the
documentation for more details.
Replaced magic numbers with #define for memory region definition in the
platform security initialization function.
Fixes ARM-software/tf-issues#149
Change-Id: Ia5d070244aae6c5288ea0e6c8e89d92859522bfe
Juan Castillo
committed
on 22 May 2014
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Merge pull request #83 from athoelke/at/tf-issues-126
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Set SCR_EL3.RW correctly before exiting bl31_main
Andrew Thoelke
committed
on 22 May 2014
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Merge pull request #85 from hliebel/hl/bl30-doc
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Improve BL3-0 documentation
Andrew Thoelke
committed
on 22 May 2014
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Allow BL3-2 platform definitions to be optional
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The generic image loading and IO FIP code no longer forces the
platform to create BL3-2 (Secure-EL1 Payload) specific
definitions. The BL3-2 loading code in bl2/bl2main.c is wrapped
by a #ifdef BL32_BASE blocks, allowing the BL3-2 definitions to
be optional. Similarly for the name_uuid array defintion in
drivers/io/io_fip.c.
Also update the porting guide to reflect this change.
The BL3-2 platform definitions remain non-configurably present
in the FVP port.
Fixes ARM-software/tf-issues#68
Change-Id: Iea28b4e94d87a31f5522f271e290919a8a955460
Dan Handley
authored
on 15 Apr 2014
Andrew Thoelke
committed
on 22 May 2014
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Use a vector table for TSP entrypoints
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The TSP has a number of entrypoints used by the TSP on different
occasions. These were provided to the TSPD as a table of function
pointers, and required the TSPD to read the entry in the table,
which is in TSP memory, in order to program the exception return
address.
Ideally, the TSPD has no access to the TSP memory.
This patch changes the table of function pointers into a vector
table of single instruction entrypoints. This allows the TSPD to
calculate the entrypoint address instead of read it.
Fixes ARM-software/tf-issues#160
Change-Id: Iec6e055d537ade78a45799fbc6f43765a4725ad3
Andrew Thoelke
committed
on 22 May 2014
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2014-05-21 |
Doc: Add the "Building the Test Secure Payload" section
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Add a section in the user guide explaining how to compile the TSP
image and include it into the FIP. This includes instructions to make
the TSP run from Trusted DRAM (rather than Trusted SRAM) on FVP.
Change-Id: I04780757a149eeb5482a12a61e821be947b882c0
Sandrine Bailleux
committed
on 21 May 2014
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fvp: Move TSP from Secure DRAM to Secure SRAM
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The TSP used to execute from secure DRAM on the FVPs because there was
not enough space in Trusted SRAM to fit it in. Thanks to recent RAM
usage enhancements being implemented, we have made enough savings for
the TSP to execute in SRAM.
However, there is no contiguous free chunk of SRAM big enough to hold
the TSP. Therefore, the different bootloader images need to be moved
around to reduce memory fragmentation. This patch keeps the overall
memory layout (i.e. keeping BL1 R/W at the bottom, BL2 at the top and
BL3-1 in between) but moves the base addresses of all the bootloader
images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest slice
of the cake since they will most probably grow the most.
A few useful numbers for reference (valid at the time of this patch):
|-----------------------|-------------------------------
| image size (debug) | extra space for the future
--------|-----------------------|-------------------------------
BL1 R/W | 20 KB | 4 KB
BL2 | 44 KB | 4 KB
BL3-1 | 108 KB | 12 KB
BL3-2 | 56 KB | 8 KB
--------|-----------------------|-------------------------------
Total | 228 KB | 28 KB = 256 KB
--------|-----------------------|-------------------------------
Although on FVPs the TSP now executes from Trusted SRAM by default,
this patch keeps the option to execute it from Trusted DRAM. This is
controlled by the build configuration 'TSP_RAM_LOCATION'.
Fixes ARM-Software/tf-issues#81
Change-Id: Ifb9ef2befa9a2d5ac0813f7f79834df7af992b94
Sandrine Bailleux
committed
on 21 May 2014
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TSP: Let the platform decide which secure memory to use
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The TSP's linker script used to assume that the TSP would
execute from secure DRAM. Although it is currently the case
on FVPs, platforms are free to use any secure memory they wish.
This patch introduces the flexibility to load the TSP into any
secure memory. The platform code gets to specify the extents of
this memory in the platform header file, as well as the BL3-2 image
limit address. The latter definition allows to check in a generic way
that the BL3-2 image fits in its bounds.
Change-Id: I9450f2d8b32d74bd00b6ce57a0a1542716ab449c
Sandrine Bailleux
committed
on 21 May 2014
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Add support for BL3-1 as a reset vector
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This change adds optional reset vector support to BL3-1
which means BL3-1 entry point can detect cold/warm boot,
initialise primary cpu, set up cci and mail box.
When using BL3-1 as a reset vector it is assumed that
the BL3-1 platform code can determine the location of
the BL3-2 images, or load them as there are no parameters
that can be passed to BL3-1 at reset.
It also fixes the incorrect initialisation of mailbox
registers on the FVP platform
This feature can be enabled by building the code with
make variable RESET_TO_BL31 set as 1
Fixes ARM-software/TF-issues#133
Fixes ARM-software/TF-issues#20
Change-Id: I4e23939b1c518614b899f549f1e8d412538ee570
Vikram Kanigiri
committed
on 21 May 2014
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Rework memory information passing to BL3-x images
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The issues addressed in this patch are:
1. Remove meminfo_t from the common interfaces in BL3-x,
expecting that platform code will find a suitable mechanism
to determine the memory extents in these images and provide
it to the BL3-x images.
2. Remove meminfo_t and bl31_plat_params_t from all FVP BL3-x
code as the images use link-time information to determine
memory extents.
meminfo_t is still used by common interface in BL1/BL2 for
loading images
Change-Id: I4e825ebf6f515b59d84dc2bdddf6edbf15e2d60f
Vikram Kanigiri
committed
on 21 May 2014
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Populate BL31 input parameters as per new spec
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This patch is based on spec published at
https://github.com/ARM-software/tf-issues/issues/133
It rearranges the bl31_args struct into
bl31_params and bl31_plat_params which provide the
information needed for Trusted firmware and platform
specific data via x0 and x1
On the FVP platform BL3-1 params and BL3-1 plat params
and its constituents are stored at the start of TZDRAM.
The information about memory availability and size for
BL3-1, BL3-2 and BL3-3 is moved into platform specific data.
Change-Id: I8b32057a3d0dd3968ea26c2541a0714177820da9
Vikram Kanigiri
committed
on 21 May 2014
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Rework handover interface between BL stages
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This patch reworks the handover interface from: BL1 to BL2 and
BL2 to BL3-1. It removes the raise_el(), change_el(), drop_el()
and run_image() functions as they catered for code paths that were
never exercised.
BL1 calls bl1_run_bl2() to jump into BL2 instead of doing the same
by calling run_image(). Similarly, BL2 issues the SMC to transfer
execution to BL3-1 through BL1 directly. Only x0 and x1 are used
to pass arguments to BL31. These arguments and parameters for
running BL3-1 are passed through a reference to a
'el_change_info_t' structure. They were being passed value in
general purpose registers earlier.
Change-Id: Id4fd019a19a9595de063766d4a66295a2c9307e1
Vikram Kanigiri
committed
on 21 May 2014
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Extend SPSR definitions for full use of ELx modes
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Extended SPSR definitions with all the fields to allow full use
of EL2/EL1 execution modes for entry points
Replaced make_spsr() with SPSR_64 macro and added SPSR_32 macro
for generating AARCH32 mode SPSR
Change-Id: I9425dda0923e8d5f03d03ddb8fa0e28392c4c61e
Vikram Kanigiri
committed
on 21 May 2014
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2014-05-20 |
Address issue 156: 64-bit addresses get truncated
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Addresses were declared as "unsigned int" in drivers/arm/peripherals/pl011/pl011.h and in function init_xlation_table. Changed to use "unsigned long" instead
Fixes ARM-software/tf-issues#156
Lin Ma
committed
on 20 May 2014
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2014-05-19 |
Improve BL3-0 documentation
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Provide some information about the expected use of BL3-0.
Fixes ARM-software/tf-issues#144
Change-Id: I5c8d59a675578394be89481ae4ec39ca37522750
Harry Liebel
committed
on 19 May 2014
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Non-Secure Interrupt support during Standard SMC processing in TSP
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Implements support for Non Secure Interrupts preempting the
Standard SMC call in EL1. Whenever an IRQ is trapped in the
Secure world we securely handover to the Normal world
to process the interrupt. The normal world then issues
"resume" smc call to resume the previous interrupted SMC call.
Fixes ARM-software/tf-issues#105
Change-Id: I72b760617dee27438754cdfc9fe9bcf4cc024858
Soby Mathew
committed
on 19 May 2014
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Enable secure timer to generate S-EL1 interrupts
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This patch enables secure physical timer during TSP initialisation and
maintains it across power management operations so that a timer
interrupt is generated every half second.
Fixes ARM-software/tf-issues#104
Fixes ARM-software/tf-issues#134
Change-Id: I66c6cfd24bd5e6035ba75ebf0f047e568770a369
Achin Gupta
committed
on 19 May 2014
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