stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver ...

The STM32 console driver was pre-pending '\r' before '\n'.
It is now managed by the framework with the flag:
CONSOLE_FLAG_TRANSLATE_CRLF.
Remove the code in driver, and add the flag for STM32MP1.

Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge changes from topic "yg/stm32mp1_wdg_updates" into integration ...

* changes:
  mmc: stm32_sdmmc2: correctly manage block size
  mmc: stm32_sdmmc2: manage max-frequency property from DT
  stm32mp1: move check_header() to common code
  stm32mp1: keep console during runtime
  stm32mp1: sp_min: initialize MMU and cache earlier
  stm32mp1: add support for LpDDR3
  stm32mp1: use a common function to check spinlock is available
  clk: stm32mp: enable RTCAPB clock for dual-core chips
  stm32mp1: check if the SoC is single core
  stm32mp1: print information about board
  stm32mp1: print information about SoC
  stm32mp1: add watchdog support

Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration

Merge "uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver" into integration

uniphier: set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver ...

This console driver sends '\r' before 'n', not after.
It works, but the convention is "\r\n" (i.e. CRLF)

Instead of fixing it in the driver, set CONSOLE_FLAG_TRANSLATE_CRLF
to leave it to the framework.

Change-Id: I2154e29313739a40dff70cfb5c0f8989136d4ad2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

mmc: stm32_sdmmc2: correctly manage block size ...

DBLOCKSIZE should be filled such as the data size is 2^DBLOCKSIZE.
Hence it is calculated with __builtin_ctz.

Change-Id: Id6b5ff9b594afc4fc523a388011beed307e6abd1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

mmc: stm32_sdmmc2: manage max-frequency property from DT ...

If the max-frequency property is provided in the device tree mmc node,
it should be managed. The max allowed frequency will be the min between
this property value and what the card can support.

Change-Id: I885b676c3300d2670a0fe4c6ecab87758b5893ad
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: move check_header() to common code ...

This function can be used on several stm32mp devices, it is then moved in
plat/st/common/stm32mp_common.c.

Change-Id: I862debe39604410f71a9ddc28713026362e9ecda
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: keep console during runtime ...

The runtime console is only kept in DEBUG configuration.

Change-Id: I0447dfcacb9a63a12bcdab7c55584d70c3220e5b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: sp_min: initialize MMU and cache earlier ...

This change enhances performance and security in BL32 stage.

Change-Id: I64df5995fc6b04f6cf42d6a00a6d3d0f602b5407
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: add support for LpDDR3 ...

This change enables LpDDR3 initialization with PMIC.

Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: use a common function to check spinlock is available ...

To use spinlocks, MMU should be enabled, as well as data cache.
A common function is created (moved from clock file).
It is then used whenever a spinlock has to be taken, in BSEC and clock
drivers.

Change-Id: I94baed0114a2061ad71bd5287a91bf7f1c6821f6
Signed-off-by: Yann Gautier <yann.gautier@st.com>

clk: stm32mp: enable RTCAPB clock for dual-core chips ...

In order to correctly manage the bring-up of non boot CPUs, the RTCAPB
clock needs to be enabled.
It controls the access to backup registers, where the CPU entrypoint
will be stored.

Change-Id: Ifeeceb4faf64bc9e0778030444f437cc0bb27272
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

stm32mp1: check if the SoC is single core ...

Among the variants of STM32MP, the STM32MP151 is a single Cortex-A7 chip.
A function is added to check the part number of the SoC.
If it corresponds to STM32MP151A or STM32MP151C, then the chip has a single
Cortex-A7.

Change-Id: Icac2015c5d03ce0bcb8e99bbaf1ec8ada34be49c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

stm32mp1: print information about board ...

On STMicroelectronics boards, the board information is stored in OTP.
This OTP is described in device tree, in BSEC board_id node.

Change-Id: Ieccbdcb048343680faac8dc577b75c67ac106f5b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

stm32mp1: print information about SoC ...

This information is located in DBGMCU registers.

Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: add watchdog support ...

Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.

The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.

An increase of BL2 size is also required when adding this new code.

Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Merge "Added SPCI to the glossary" into integration

Merge "Move assembly newline function into common debug code" into integration

Added SPCI to the glossary ...

Change-Id: I576ae161477f4a69336d15a7741e566bb103124a
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>

Move assembly newline function into common debug code ...

Printing a newline is a relatively common functionality for code to want
to do. Therefore, this patch now moves this function into a common part
of the code that anyone can use.

Change-Id: I2cad699fde00ef8d2aabf8bf35742ddd88d090ba
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration

Merge "tegra: add support for multi console interface" into integration

Merge "AArch64: Disable Secure Cycle Counter" into integration

AArch64: Disable Secure Cycle Counter ...

This patch fixes an issue when secure world timing information
can be leaked because Secure Cycle Counter is not disabled.
For ARMv8.5 the counter gets disabled by setting MDCR_El3.SCCD
bit on CPU cold/warm boot.
For the earlier architectures PMCR_EL0 register is saved/restored
on secure world entry/exit from/to Non-secure state, and cycle
counting gets disabled by setting PMCR_EL0.DP bit.
'include\aarch64\arch.h' header file was tided up and new
ARMv8.5-PMU related definitions were added.

Change-Id: I6f56db6bc77504634a352388990ad925a69ebbfa
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "plat/arm: Introduce corstone700 platform." into integration

Merge "rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*" into integration

plat/arm: Introduce corstone700 platform. ...

This patch adds support for Corstone-700 foundation IP, which integrates
both Cortex-M0+ and Cortex-A(Host) processors in one handy, flexible
subsystem.
This is an example implementation of Corstone-700 IP host firmware.

Cortex-M0+ will take care of boot stages 1 and 2(BL1/BL2) as well as
bringing Host out RESET. Host will start execution directly from BL32 and
then will jump to Linux.

It is an initial port and additional features are expected to be added
later.

Change-Id: I7b5c0278243d574284b777b2408375d007a7736e
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

Merge "rcar_gen3: plat: Factor out PRR_ macros into rcar_def.h" into integration

Merge "intel: agilex: HMC driver calculate DDR size" into integration