Enable secure memory support for FVPs ...

- Use the TrustZone controller on Base FVP to program DRAM access
  permissions. By default no access to DRAM is allowed if
  'secure memory' is enabled on the Base FVP.
- The Foundation FVP does not have a TrustZone controller but instead
  has fixed access permissions.
- Update FDTs for Linux to use timers at the correct security level.
- Starting the FVPs with 'secure memory' disabled is also supported.

Limitations:
Virtio currently uses a reserved NSAID. This will be corrected in
future FVP releases.

Change-Id: I0b6c003a7b5982267815f62bcf6eb82aa4c50a31

Add TrustZone (TZC-400) driver ...

The TZC-400 performs security checks on transactions to memory or
peripherals. Separate regions can be created in the address space each
with individual security settings.

Limitations:
This driver does not currently support raising an interrupt on access
violation.

Change-Id: Idf8ed64b4d8d218fc9b6f9d75acdb2cd441d2449

Merge pull request #43 from danh-arm/dh/tf-issues#129 ...

Move console.c to pl011 specific driver location

Merge pull request #44 from danh-arm/dh/tf-issues#136 ...

Remove redundant code from bl1_plat_helpers.S

Merge pull request #45 from danh-arm/dh/tf-issues#114 ...

Rename FVP "mmap" array to avoid name confusion

Remove redundant code from bl1_plat_helpers.S ...

Remove redundant code in plat_secondary_cold_boot_setup() in
plat/fvp/aarch64/bl1_plat_helpers.S.

Fixes ARM-software/tf-issues#136

Change-Id: I98c0a46d95cfea33125e34e609c83dc2c97cd86e

Merge pull request #40 from athoelke/at/up-stacks-76-v2 ...

Allocate single stacks for BL1 and BL2 (v2)

Allocate single stacks for BL1 and BL2 ...

The BL images share common stack management code which provides
one coherent and one cacheable stack for every CPU. BL1 and BL2
just execute on the primary CPU during boot and do not require
the additional CPU stacks. This patch provides separate stack
support code for UP and MP images, substantially reducing the
RAM usage for BL1 and BL2 for the FVP platform.

This patch also provides macros for declaring stacks and
calculating stack base addresses to improve consistency where
this has to be done in the firmware.

The stack allocation source files are now included via
platform.mk rather than the common BLx makefiles. This allows
each platform to select the appropriate MP/UP stack support
for each BL image.

Each platform makefile must be updated when including this
commit.

Fixes ARM-software/tf-issues#76

Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632

Rename FVP "mmap" array to avoid name confusion ...

Rename the array "mmap" in plat/fvp/aarch64/plat_common.c to
"fvp_mmap", to avoid confusion with the array of the same name
in lib/arch/aarch64/xlat_tables.c

Fixes ARM-software/tf-issues#114

Change-Id: I61478c0070aa52d5dcf5d85af2f353f56c060cfb

Merge pull request #36 from athoelke/at/gc-sections-80 ...

Using GCC --gc-sections to eliminate unused code and data

Move console.c to pl011 specific driver location ...

Rename drivers/console/console.c to
drivers/arm/peripherals/pl011/pl011_console.c. This makes it clear
that this is a pl011 specific console implementation.

Fixes ARM-software/tf-issues#129

Change-Id: Ie2f8109602134c5b86993e32452c70734c45a3ed

Merge pull request #38 from sandrine-bailleux/sb/tf-issue-125 ...

Fix system counter initialisation

Define frequency of system counter in platform code ...

BL3-1 architecture setup code programs the system counter frequency
into the CNTFRQ_EL0 register. This frequency is defined by the
platform, though. This patch introduces a new platform hook that
the architecture setup code can call to retrieve this information.
In the ARM FVP port, this returns the first entry of the frequency
modes table from the memory mapped generic timer.

All system counter setup code has been removed from BL1 as some
platforms may not have initialized the system counters at this stage.
The platform specific settings done exclusively in BL1 have been moved
to BL3-1. In the ARM FVP port, this consists in enabling and
initializing the System level generic timer. Also, the frequency change
request in the counter control register has been set to 0 to make it
explicit it's using the base frequency. The CNTCR_FCREQ() macro has been
fixed in this context to give an entry number rather than a bitmask.

In future, when support for firmware update is implemented, there
is a case where BL1 platform specific code will need to program
the counter frequency. This should be implemented at that time.

This patch also updates the relevant documentation.

It properly fixes ARM-software/tf-issues#24

Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b

Revert "Move architecture timer setup to platform-specific code" ...

This reverts commit 1c297bf
because it introduced a bug: the CNTFRQ_EL0 register was no
longer programmed by all CPUs.  bl31_platform_setup() function
is invoked only in the cold boot path and consequently only
on the primary cpu.

A subsequent commit will correctly implement the necessary changes
to the counter frequency setup code.

Fixes ARM-software/tf-issues#125

Conflicts:

	docs/firmware-design.md
	plat/fvp/bl31_plat_setup.c

Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54

Merge pull request #35 from sandrine-bailleux/sb/add-missing-include-guard ...

Add missing #include guard in xlat_tables.h

Merge pull request #34 from danh-arm/dh/new-integration-process ...

Update contributing.md with new integration process

Add missing #include guard in xlat_tables.h ...

Change-Id: I7272a800accb7de71cbbf6b715a43061bbf79f8c

Update contributing.md with new integration process ...

Contributions will now be merged into an ARM Trusted Firmware
integration branch on GitHub instead of via an ARM internal
branch.

Place assembler functions in separate sections ...

This extends the --gc-sections behaviour to the many assembler
support functions in the firmware images by placing each function
into its own code section. This is achieved by creating a 'func'
macro used to declare each function label.

Fixes ARM-software/tf-issues#80

Change-Id: I301937b630add292d2dec6d2561a7fcfa6fec690

Use --gc-sections during link ...

All common functions are being built into all binary images,
whether or not they are actually used. This change enables the
use of -ffunction-sections, -fdata-sections and --gc-sections
in the compiler and linker to remove unused code and data from
the images.

Change-Id: Ia9f78c01054ac4fa15d145af38b88a0d6fb7d409

Fix build failure due to a typo in TSPD code ...

This patch fixes a build failure when TSPD support is included. The failure was
due to a missing semi-colon at the end of a C statement in tspd_common.c

Change-Id: I8fbd0d500bd9145b15f862b8686e570b80fcce8c

Build system: Trigger dependency checking only for build targets ...

The Makefile used to specify a blacklist of rules for which
dependency checking must not be triggered.  This list included
cleaning rules only, whereas all other non-build targets (e.g.
help, checkpatch, etc.) should also be included.

This approach seems a bit fragile because it is easy to forget
some non-building rules in the blacklist, as the experience
showed us.  It is more robust to specify a whitelist of rules
for which dependency checking is required.

Fixes ARM-software/tf-issues#112

Change-Id: I030c405abb35972a726a5200396430316d18f963

Initialise UART console in all bootloader stages ...

This patch reworks the console driver to ensure that each bootloader stage
initializes it independently. As a result, both BL3-1 and BL2 platform code
now calls console_init() instead of relying on BL1 to perform console setup

Fixes ARM-software/tf-issues#120

Change-Id: Ic4d66e0375e40a2fc7434afcabc8bbb4715c14ab

Move console functions out of pl011.c ...

This commit isolates the accessor functions in pl011.c and builds
a wrapper layer for console functions.

This also modifies the console driver to use the pl011 FIFO.

Fixes ARM-software/tf-issues#63

Change-Id: I3b402171cd14a927831bf5e5d4bb310b6da0e9a8

Build system: Remove last traces of 'PLAT=all' ...

It used to be possible to build all bootloader binaries for all platforms 
using 'PLAT=all'. This feature has been removed but there are still some 
traces of its existence. This patch removes them.

Change-Id: Ic671a5c20c5b64acbd0a912d2e4db8f9d9574610

Fix build by correcting asm helper function usage in TSPD ...

This patch fixes a regression failure due to the use of functions by the 
TSPD code which access system registers with partially qualified names. 
These functions had been removed in an earlier patch. The relevant code 
has been updated to access these registers with their fully qualified 
names.

Fixes ARM-software/tf-issues#119

Change-Id: Ide1bc5036e1b8164a42f7b7fe86186ad860e0ef9

Separate out BL2, BL3-1 and BL3-2 early exception vectors from BL1 ...

bl1/aarch64/early_exceptions.S used to be re-used by BL2, BL3-1 and
BL3-2.  There was some early SMC handling code in there that was not
required by the other bootloader stages.  Therefore this patch
introduces an even simpler exception vector source file for BL2,
BL3-1 and BL3-2.

Fixes ARM-software/tf-issues#38

Change-Id: I0244b80e9930b0f8035156a0bf91cc3e9a8f995d

Move per cpu exception stack in BL31 to tzfw_normal_stacks ...

Fixes ARM-software/tf-issues#70

Change-Id: I7f024f173fbdecd315076f528b05d6295aff7276

Add standby state support in PSCI cpu_suspend api ...

This patch adds support in the generic PSCI implementation to call a
platform specific function to enter a standby state using an example
implementation in ARM FVP port

Fixes ARM-software/tf-issues#94
Change-Id: Ic1263fcf25f28e09162ad29dca954125f9aa8cc9

Semihosting: Fix file mode to load binaries on Windows ...

Trusted firmware binaries loaded via semihosting used to be
opened using 'r' mode (i.e. read mode).  This is fine on POSIX
conforming systems (including Linux) but for Windows it also means
that the file should be opened in text mode. 'rb' mode must be
specified instead for binary mode.  On POSIX conforming systems,
'rb' mode is equivalent to 'r' mode so it does no harm.

Fixes ARM-software/tf-issues#69

Change-Id: Ifa53f2ecfd765f572dea5dd73191f9fe2b2c2011