Merge changes from topic "raspberry-pi-4-support" into integration ...

* changes:
  Add fdt_add_reserved_memory() helper function
  qemu: Move and generalise FDT PSCI fixup

Merge changes from topic "raspberry-pi-4-support" into integration ...

* changes:
  rpi3: Move rng driver to drivers
  rpi3: Move VC mailbox driver into generic drivers directory
  rpi3: Move rpi3_hw.h header file to include/rpi_hw.h

Merge "rpi3: Add "rpi" platform directory" into integration

Add fdt_add_reserved_memory() helper function ...

If a firmware component like TF-A reserves special memory regions for
its own or secure payload services, it should announce the location and
size of those regions to the non-secure world. This will avoid
disappointment when some rich OS tries to acccess this memory, which
will likely end in a crash.

The traditional way of advertising reserved memory using device tree is
using the special memreserve feature of the device tree blob (DTB).
However by definition those regions mentioned there do not prevent the
rich OS to map this memory, which may lead to speculative accesses to
this memory and hence spurious bus errors.

A safer way of carving out memory is to use the /reserved-memory node as
part of the normal DT structure. Besides being easier to setup, this
also defines an explicit "no-map" property to signify the secure-only
nature of certain memory regions, which avoids the rich OS to
accidentally step on it.

Add a helper function to allow platform ports to easily add a region.

Change-Id: I2b92676cf48fd3bdacda05b5c6b1c7952ebed68c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

rpi3: Move rng driver to drivers ...

To allow sharing the driver between the RPi3 and RPi4, move the random
number generator driver into the generic driver directory.

Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

rpi3: Add "rpi" platform directory ...

With the incoming support for the Raspberry Pi 4 boards, one directory
to serve both versions will not end up well.

Create an additional layer by inserting a "rpi" directory betweeen /plat
and rpi3, so that we can more easily share or separate files between the
two later.

Change-Id: I75adbb054fe7902f34db0fd5e579a55612dd8a5f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

qemu: Move and generalise FDT PSCI fixup ...

The QEMU platform port scans its device tree to advertise PSCI as the
CPU enable method. It does this by scanning *every* node in the DT and
check whether its compatible string starts with "arm,cortex-a". Then it
sets the enable-method to PSCI, if it doesn't already have one.

Other platforms might want to use this functionality as well, so let's
move it out of the QEMU platform directory and make it more robust by
fixing some shortcomings:
- A compatible string starting with a certain prefix is not a good way
to find the CPU nodes. For instance a "arm,cortex-a72-pmu" node will
match as well and is in turn favoured with an enable-method.
- If the DT already has an enable-method, we won't change this to PSCI.

Those two issues will for instance fail on the Raspberry Pi 4 DT.
To fix those problems, we adjust the scanning method:
The DT spec says that all CPU nodes are subnodes of the mandatory
/cpus node, which is a subnode of the root node. Also each CPU node has
to have a device_type = "cpu" property. So we find the /cpus node, then
scan for a subnode with the proper device_type, forcing the
enable-method to "psci".
We have to restart this search after a property has been patched, as the
node offsets might have changed meanwhile.

This allows this routine to be reused for the Raspberry Pi 4 later.

Change-Id: I00cae16cc923d9f8bb96a9b2a2933b9a79b06139
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

rpi3: Move VC mailbox driver into generic drivers directory ...

To allow sharing the driver between the RPi3 and RPi4, move the mailbox
driver into the generic driver directory.

Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

rpi3: Move rpi3_hw.h header file to include/rpi_hw.h ...

With the advent of Raspberry Pi 4 support, we need to separate some
board specific headers between the RPi3 and RPi4.
Rename and move the "rpi3_hw.h" header, so that .c files just include
rpi_hw.h, and automatically get the correct version.

Change-Id: I03b39063028d2bee1429bffccde71dddfe2dcde8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Merge "Refactor ARMv8.3 Pointer Authentication support code" into integration

Merge "Add Linux DTS files for 32 bit threaded FVPs" into integration

Merge "Modify FVP makefile for cores that support both AArch64/32" into integration

Merge "amlogic: console: Move console driver to common directory" into integration

Refactor ARMv8.3 Pointer Authentication support code ...

This patch provides the following features and makes modifications
listed below:
- Individual APIAKey key generation for each CPU.
- New key generation on every BL31 warm boot and TSP CPU On event.
- Per-CPU storage of APIAKey added in percpu_data[]
  of cpu_data structure.
- `plat_init_apiakey()` function replaced with `plat_init_apkey()`
  which returns 128-bit value and uses Generic timer physical counter
  value to increase the randomness of the generated key.
  The new function can be used for generation of all ARMv8.3-PAuth keys
- ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`.
- New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions
  generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively;
  pauth_disable_el1()` and `pauth_disable_el3()` functions disable
  PAuth for EL1 and EL3 respectively;
  `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from
  cpu-data structure.
- Combined `save_gp_pauth_registers()` function replaces calls to
  `save_gp_registers()` and `pauth_context_save()`;
  `restore_gp_pauth_registers()` replaces `pauth_context_restore()`
  and `restore_gp_registers()` calls.
- `restore_gp_registers_eret()` function removed with corresponding
  code placed in `el3_exit()`.
- Fixed the issue when `pauth_t pauth_ctx` structure allocated space
  for 12 uint64_t PAuth registers instead of 10 by removal of macro
  CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h`
  and assigning its value to CTX_PAUTH_REGS_END.
- Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions
  in `msr	spsel`  instruction instead of hard-coded values.
- Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI.

Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration

Merge "Assert if power level value greater then PSCI_INVALID_PWR_LVL" into integration

Merge changes from topic "jc/rsa-pkcs" into integration ...

* changes:
  Remove RSA PKCS#1 v1.5 support from cert_tool
  Add documentation for new KEY_SIZE option
  Add cert_create tool support for RSA key sizes
  Support larger RSA key sizes when using MBEDTLS

Merge changes I08cf22df,I535ee414,Ie84cfc96,I8c35ce4e,If7649764, ... into integration ...

* changes:
  mediatek: mt8183: Support coreboot configuration
  mediatek: mt8183: support system reset
  mediatek: mt8183: pass platform parameters
  mediatek: mt8183: add GPIO driver
  mediatek: mt8183: support system off
  mediatek: mt8183: support CPU hotplug
  mediatek: mt8183: refine GIC driver

Merge "Unify type of "cpu_idx" across PSCI module." into integration

Merge "mediatek: mt8173: apply MULTI_CONSOLE framework" into integration

Unify type of "cpu_idx" across PSCI module. ...

cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places. This change is to unify the
cpu_idx as `unsigned int` as underlying API;s `plat_my_core_pos`
returns `unsigned int`

It was discovered via coverity issue CID 354715

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I4f0adb0c596ff1177210c5fe803bff853f2e54ce

amlogic: console: Move console driver to common directory ...

The code managing the console is the same for all the platforms
currently supported. Since it is unlikely to change in the future move
the code to an external file in the common directory.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I6df555ea82d483b4f08a4a1e2cb0a7488fbaa015

mediatek: mt8173: apply MULTI_CONSOLE framework ...

- Switch uart driver from Mediatek 8250 to TI 16550
- Enable MULTI_CONSOLE

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ie3948d9e64d05d29a1f69592792e277b680c4ed4

Merge "Add python configuration for editorconfig" into integration

Merge "Tegra: memctrl_v2: fix "overflow before widen" coverity issue" into integration

Merge "Invalidate dcache build option for bl2 entry at EL3" into integration

Remove RSA PKCS#1 v1.5 support from cert_tool ...

Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed
in SHA fe199e3, however, cert_tool is still able to generate
certificates in that form. This patch fully removes the ability for
cert_tool to generate these certificates.

Additionally, this patch also fixes a bug where the issuing certificate
was a RSA and the issued certificate was EcDSA. In this case, the issued
certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per
PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now
that PKCS#1 v1.5 support is removed, all certificates that are signed
with RSA now use the more modern padding scheme.

Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Add documentation for new KEY_SIZE option ...

This patch adds documentation for the new KEY_SIZE build option that is
exposed by cert_create, and instructions on how to use it.

Change-Id: I09b9b052bfdeeaca837e0f0026e2b01144f2472c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Add cert_create tool support for RSA key sizes ...

cert_tool is now able to accept a command line option for specifying the
key size. It now supports the following options: 1024, 2048 (default),
3072 and 4096. This is also modifiable by TFA using the build flag
KEY_SIZE.

Change-Id: Ifadecf84ade3763249ee8cc7123a8178f606f0e5
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Support larger RSA key sizes when using MBEDTLS ...

Previously, TF-A could not support large RSA key sizes as the
configuration options passed to MBEDTLS prevented storing and performing
calculations with the larger, higher-precision numbers required. With
these changes to the arguments passed to MBEDTLS, TF-A now supports
using 3072 (3K) and 4096 (4K) keys in certificates.

Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>