plat: intel: set DRVSEL and SMPLSEL for DWMMC
...
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
Tien Hock Loh
authored
on 11 May 2020
Manish Pandey
committed
on 8 Jun 2020