Tegra194: organize the memory/mmio map to make it linear ...

This patch organizes the platform memory/mmio map, so that the base
addresses for the apertures line up in ascending order. This makes
it easier for the xlat_tables_v2 library to create mappings for each
mmap_add_region call.

Change-Id: Ie1938ba043820625c9fea904009a3d2ccd29f7b3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: support for boot params wider than 32-bits ...

The previous bootloader is not able to pass boot params wider than
32-bits due to an oversight in the scratch register being used. A
new secure scratch register #75 has been assigned to pass the higher
bits.

This patch adds support to parse the higher bits from scratch #75
and use them in calculating the base address for the location of
the boot params.

Scratch #75 format
====================
31:16 - bl31_plat_params high address
15:0 - bl31_params high address

Change-Id: Id53c45f70a9cb370c776ed7c82ad3f2258576a80
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra194: memctrl: set reorder depth limit for PCIE blocks ...

HW bug in third party PCIE IP - PCIE datapath hangs when there are
more than 28 outstanding requests on data backbone for x1 controller.

Suggested SW WAR is to limit reorder_depth_limit to 16 for
PCIE 1W/2AW/3W clients.

Change-Id: Id5448251c35d2a93f66a8b5835ae4044f5cef067
Signed-off-by: Puneet Saxena <puneets@nvidia.com>

Tegra194: memctrl: update mss reprogramming as HW PROD settings ...

Memory clients are divided in to ISO/NonISO/Order/Unordered/Low
BW/High BW. Based on the client types, HW team recommends, different
memory ordering settings, IO coherency settings and SMMU register settings
for optimized performance of the MC clients.

For example ordered ISO clients should be set as strongly ordered and
should bypass SCF and directly access MC hence set as
FORCE_NON_COHERENT. Like this there are multiple recommendations
for all of the MC clients.

This change sets all these MC registers as per HW spec file.

Change-Id: I8a8a0887cd86bf6fe8ac7835df6c888855738cd9
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: memctrl: Disable PVARDC coalescer ...

Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0RDC and PVA1RDC.

Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>

Tegra194: toggle SE clock during context save/restore ...

This patch adds support to toggle SE clock, using the bpmp_ipc
interface, to enable SE context save/restore. The SE sequence mostly
gets called during System Suspend/Resume.

Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7
Signed-off-by: steven kao <skao@nvidia.com>

Tegra194: memctrl: force viw and vifalr/w transactions as non-coherent ...

Force memory transactions from viw and viflar/w as non-coherent from
no-override. This is necessary as iso clients shouldn't use coherent
path and stage-2 smmu mappings won't mark transactions as non-coherent.
For native case, no-override works. But, not for virtualization case.

Change-Id: I1a8fc17787c8d0f8579bdaeeb719084993e27276
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

Tegra194: memctrl: fix bug in client order id reg value generation ...

Client order id reset values are incorrectly and'ed with
mc_client_order_id macro, which resulted in getting reg value as
always zero. Updated mc_client_order_id macro to avoid and'ing outside
the macro, to take the reg value and update specific bit field
as necessary.

Change-Id: I880be6e4291d7cd58cf70d7c247a4044e57edd9e
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

Tegra194: memctrl: enable mc coalescer ...

This patch enable the Memory Controller's "Coalescer" feature to
improve performance of memory transactions.

Change-Id: I50ba0354116284f85d9e170c293ce77e9f3fb4d8
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: update scratch registers used to read boot parameters ...

This patch changes SCRATCH_BOOT_PARAMS_ADDR macro to use SECURE_SCRATCH_RSV81
instead of SECURE_SCRATCH_RSV44. The previous level bootloader changed this
setting, so update here to keep both components in sync.

Change-Id: I4e0c1b54fc69482d5513a8608d0bf616677e1bdd
Signed-off-by: steven kao <skao@nvidia.com>

Tegra: include: fix violations of MISRA Rule 21.1 ...

This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185

Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration

plat: nvidia: remove spurious UTF-8 characters at top of platform files ...

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423

Remove redundant declarations. ...

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Tegra194: introduce tegra_mc_def.h ...

This patch introduces memory controller register defines
for Tegra194 platforms.

Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: 40-bit wide memory address space ...

This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.

Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra194: add support to reset GPU ...

This patch adds macros, to define registers required to support GPU
reset, for Tegra194 SoCs.

Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra194: memctrl: fix logic to check TZDRAM config register access ...

This patch fixes the logic to check if the previous bootloader has
disabled access to the TZDRAM configuration registers. The polarity
for the bit was incorrect in the previous check.

Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra: introduce plat_enable_console() ...

This patch introduces the 'plat_enable_console' handler to allow
the platform to enable the right console. Tegra194 platform supports
multiple console, while all the previous platforms support only one
console.

For Tegra194 platforms, the previous bootloader checks the platform
config and sets the uart-id boot parameter, to 0xFE. On seeing this
boot parameter, the platform port uses the proper memory aperture
base address to communicate with the SPE. This functionality is
currently protected by a platform macro, ENABLE_CONSOLE_SPE.

Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: include: drivers: introduce spe.h ...

This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799

Tegra194: memctrl: platform handler for TZDRAM setup ...

This patch provides the platform with flexibility to perform custom
steps during TZDRAM setup. Tegra194 platforms checks if the config
registers are locked and TZDRAM setup has already been done by the
previous bootloaders, before setting up the fence.

Change-Id: Ifee7077d4b46a7031c4568934c63e361c53a12e3
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra194: save system suspend entry marker to TZDRAM ...

This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.

The Tegra194 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.

Change-Id: I29d73f1693c89ebc8d19d7abb1df1e460eb5558e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: helper functions for CPU rst handler and SMMU ctx offset ...

This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.

Change-Id: I95e2862fe37ccad00fa48ec165c6e4024df01147
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: cleanup references to Tegra186 ...

This patch cleans up all references to the Tegra186 family of SoCs.

Change-Id: Ife892caba5f2523debacedf8ec465289def9afd0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: drivers: SE and RNG1/PKA1 context save support ...

This patch adds the driver, to implement the programming sequence to
save/restore hardware context, during System Suspend/Resume.

Change-Id: If851a81cd4e699b58a0055d0be7f145759792ee9
Signed-off-by: Steven Kao <skao@nvidia.com>
Signed-off-by: Jeff Tsai <jefft@nvidia.com>

Tegra194: rename secure scratch register macros ...

This patch renames all the secure scratch registers to reflect
their usage.

This is a list of all the macros being renamed:

- SECURE_SCRATCH_RSV44_* -> SCRATCH_BOOT_PARAMS_ADDR_*
- SECURE_SCRATCH_RSV97 -> SCRATCH_SECURE_BOOTP_FCFG
- SECURE_SCRATCH_RSV99_* -> SCRATCH_SMMU_TABLE_ADDR_*
- SECURE_SCRATCH_RSV109_* -> SCRATCH_RESET_VECTOR_*

Change-Id: I838ece3da39bc4be8f349782e99bac777755fa39
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra194: fix defects flagged by MISRA scan ...

Main fixes:

Fix invalid use of function pointer [Rule 1.3]

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: I65a2b33e59aebb7746bd31544c79d57c3d5678c5
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra194: remove the GPU reset register macro ...

There is a possibility that once we have checked that the GPU is
in reset, some component can get still it out of reset.
This patch removes the check register macro.

Change-Id: Idbbba36f97e37c7db64ab9e42848a040ccd05acd
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra194: MC registers to allow CPU accesses to TZRAM ...

This patch adds MC registers and macros to allow CPU to access
TZRAM.

Change-Id: I46da526aa760c89714f8898591981bb6cfb29237
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: memctrl: platform handlers to reprogram MSS ...

Introduce platform handlers to reprogram the MSS settings.

Change-Id: Ibb9a5457d1bad9ecccea619d69a62bed3bf7d861
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>