Tegra194: store TZDRAM base/size to scratch registers ...

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra194: fix warnings for extra parentheses ...

armclang displays warnings for extra parentheses, leading to
build failures as warnings are treated as errors.
This patch removes the extra parentheses to fix this issue.

Change-Id: Id2fd6a3086590436eecabc55502f40752a018131
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra186: store TZDRAM base/size to scratch registers ...

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: Ic70914cb958249f06cb58025a24d13734a85e16e
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: add SE support to generate SHA256 of TZRAM ...

The BL3-1 firmware code is stored in TZSRAM on Tegra186 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store SE SHA256 hash-result to PMC scratch registers.

Change-Id: Ib487d5629225d3d99bd35d44f0402d6d3cf27ddf
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra186: add support for bpmp_ipc driver ...

This patch enables the bpmp-ipc driver for Tegra186 platforms,
to ask BPMP firmware to toggle SE clock.

Change-Id: Ie63587346c4d9b7e54767dbee17d0139fa2818ae
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

Tegra210: disable ERRATA_A57_829520 ...

ERRATA_A57_829520 disables "indirect branch prediction" for
EL1 on cpu reset, leading to 15% drop in CPU performance
with coremark benchmarks.

Tegra210 already has a hardware fix for ARM BUG#829520,so
this errata is not needed.

This patch disables the errata to get increased performance
numbers.

Change-Id: I0b42e8badd19a8101f6a55d80eb2d953597d3c20
Signed-off-by: Mithun Maragiri <mmaragiri@nvidia.com>

Tegra194: memctrl: add support for MIU4 and MIU5 ...

This patch adds support for memqual miu 4,5.

The MEMQUAL engine has miu0 to miu7 in which miu6 and
miu7 is hardwired to bypass SMMU. So only miu0 to miu5
support is provided.

Change-Id: Ib350334eec521e65f395f1c3205e2cdaf464ebea
Signed-off-by: Pravin <pt@nvidia.com>

Tegra194: memctrl: remove support to reconfigure MSS ...

As bpmp-fw is running at the same time as ATF, and
the mss client reconfiguration sequence involves performing
a hot flush resets on bpmp, there is a chance that bpmp-fw is
trying to perform accesses while the hot flush is active.

Therefore, the mss client reconfigure has been moved to
System Suspend resume fw and bootloader, and it can be
removed from here.

Change-Id: I34019ad12abea9681f5e180af6bc86f2c4c6fc74
Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>

Tegra210: SE: add context save support ...

Tegra210B01 SoCs support atomic context save for the two SE
hardware engines. Tegra210 SoCs have support for only one SE
engine and support a software based save/restore mechanism
instead.

This patch updates the SE driver to make this change.

Change-Id: Ia5e5ed75d0fe011f17809684bbc2ed2338925946
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

Tegra210: update the PMC blacklisted registers ...

Update the list to include PMC registers that the NS world cannot
access even with smc calls.

Change-Id: I588179b56ebc0c29200b55e6d61535fd3a7a3b7e
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

spe: Use generic console_t data structure ...

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I75dbfafb67849833b3f7b5047e237651e3f553cd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

LS 16550: Use generic console_t data structure ...

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: Ifd6aff1064ba1c3c029cdd8a83f715f7a9976db5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

16550: Use generic console_t data structure ...

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Tegra: handler to check support for System Suspend ...

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: platform handler to relocate BL32 image ...

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: secure PMC hardware block ...

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.

The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.

Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

Tegra194: memctrl: lock mc stream id security config ...

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.

- ISPRA
- ISPFALR
- ISPFALW
- ISPWA
- ISPWA1
- ISPWB
- XUSB_DEVR
- XUSB_DEVW
- XUSB_HOSTR
- XUSB_HOSTW
- VIW
- VIFALR
- VIFALW

Change-Id: I66192b228a0a237035938f498babc0325764d5df
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra210: resume PMC hardware block for all platforms ...

The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause problems for devices that do not support this
firmware.

This patch fixes this logic and resumes the PMC block even if
the sc7entry-fw is not present on the device.

Change-Id: I6f0eb7878126f624ea98392f583ed45a231d27db
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra186: enable higher performance non-cacheable load forwarding ...

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c9679602ecb47b53
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: enable higher performance non-cacheable load forwarding ...

This patch enables higher performance non-cacheable load forwarding for
Tegra210 platforms.

Change-Id: I11d0ffc09aca97d37386f283f2fbd2483d51fd28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: mce: declare nvg_roc_clean_cache_trbits() ...

This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

Change-Id: I313556f6799792fc0141afb5822cc157db80bc47
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: memctrl: lock stream id security config ...

Tegra186 is in production so lock stream id security configs
for all the clients.

Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: remove support for simulated system suspend ...

This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now.

Change-Id: I9ed1b002886fed7bbc3d890a82d6cad67e900bae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: mce: fix multiple MISRA issues ...

This patch fixes violations of the following MISRA rules

* Rule 8.5  "An external object or function shall be declared once in
             one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
             object with a narrower essential type or of a different
             esential type category"

Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: se: fix multiple MISRA issues ...

This patch fixes violations for the following MISRA rules

* Rule 8.4  "A compatible declaration shall be visible when an object or
             function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
             conversions are perdormed shall have the same essential type
             category"
* Rule 17.7 "The value returned by a function having non-void return
             type shall be used"

Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: compile PMC driver for Tegra132/Tegra210 platforms ...

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.

As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.

Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: remove weakly defined PSCI platform handlers ...

This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.

Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: remove weakly defined platform setup handlers ...

This patch converts the weakly defined platform setup handlers into
actual platform specific handlers to improve code coverage numbers
and some MISRA defects.

The weakly defined handlers never get executed thus resulting in
lower coverage - function, function calls, statements, branches
and pairs.

Change-Id: I02f450f66b5754a90d934df4d76eb91459fca5f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Enable -Wredundant-decls warning check ...

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Tegra194: enable spe-console functionality ...

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>