2014-07-28 |
Introduce asm console functions in TF
...
This patch replaces the pl011 console family of functions
with their equivalents defined in assembly. The baud rate is
defined by the PL011_BAUDRATE macro and IBRD and FBRD values
for pl011 are computed statically. This patch will enable
us to invoke the console functions without the C Runtime Stack.
Change-Id: Ic3f7b7370ded38bf9020bf746b362081b76642c7
Soby Mathew
committed
on 28 Jul 2014
|
Simplify management of SCTLR_EL3 and SCTLR_EL1
...
This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.
Fixes ARM-software/tf-issues#226
Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069
Achin Gupta
committed
on 28 Jul 2014
|
2014-07-25 |
Add support for printing version at runtime
...
Print out Trusted Firmware version at runtime at each BL stage.
Message consists of TF version as defined statically in the Makefile
(e.g. v0.4), build mode (debug|release) and a customizable build
string:
1. By defining BUILD_STRING in command line when building TF
2. Default string is git commit ID
3. Empty if git meta-data is not available
Fixes ARM-software/tf-issues#203
Change-Id: I5c5ba438f66ab68810427d76b49c5b9177a957d6
Juan Castillo
authored
on 30 Jun 2014
Dan Handley
committed
on 25 Jul 2014
|
Implement a leaner printf for Trusted Firmware
...
This patch implements a "tf_printf" which supports only the commonly
used format specifiers in Trusted Firmware, which uses a lot less
stack space than the stdlib printf function.
Fixes ARM-software/tf-issues#116
Change-Id: I7dfa1944f4c1e634b3e2d571f49afe02d109a351
Soby Mathew
committed
on 25 Jul 2014
|
2014-07-19 |
Remove coherent stack usage from the warm boot path
...
This patch uses stacks allocated in normal memory to enable the MMU early in the
warm boot path thus removing the dependency on stacks allocated in coherent
memory. Necessary cache and stack maintenance is performed when a cpu is being
powered down and up. This avoids any coherency issues that can arise from
reading speculatively fetched stale stack memory from another CPUs cache. These
changes affect the warm boot path in both BL3-1 and BL3-2.
The EL3 system registers responsible for preserving the MMU state are not saved
and restored any longer. Static values are used to program these system
registers when a cpu is powered on or resumed from suspend.
Change-Id: I8357e2eb5eb6c5f448492c5094b82b8927603784
Achin Gupta
committed
on 19 Jul 2014
|
Make enablement of the MMU more flexible
...
This patch adds a 'flags' parameter to each exception level specific function
responsible for enabling the MMU. At present only a single flag which indicates
whether the data cache should also be enabled is implemented. Subsequent patches
will use this flag when enabling the MMU in the warm boot paths.
Change-Id: I0eafae1e678c9ecc604e680851093f1680e9cefa
Achin Gupta
committed
on 19 Jul 2014
|
2014-07-11 |
Merge pull request #162 from jcastillo-arm/jc/tf-issues/194
...
Allow FP register context to be optional at build time
danh-arm
committed
on 11 Jul 2014
|
Merge pull request #164 from sandrine-bailleux/sb/bl30-support-v2
...
Add support for BL3-0 image (v2)
danh-arm
committed
on 11 Jul 2014
|
2014-07-10 |
Add support for BL3-0 image
...
- Add support for loading a BL3-0 image in BL2. Information about
memory extents is populated by platform-specific code. Subsequent
handling of BL3-0 is also platform specific.
The BL2 main function has been broken down to improve readability.
The BL3-2 image is now loaded before the BL3-3 image to align with
the boot flow.
- Build system: Add support for specifying a BL3-0 image that will be
included into the FIP image.
- IO FIP driver: Add support for identifying a BL3-0 image inside a
FIP image.
- Update the documentation to reflect the above changes.
Change-Id: I067c184afd52ccaa86569f13664757570c86fc48
Sandrine Bailleux
committed
on 10 Jul 2014
|
Merge pull request #157 from sandrine-bailleux/sb/tf-issue-109
...
TF issue 109
danh-arm
committed
on 10 Jul 2014
|
Merge pull request #146 from danh-arm/dh/refactor-fvp-gic
...
Refactor fvp config and gic code
danh-arm
committed
on 10 Jul 2014
|
Allow FP register context to be optional at build time
...
CTX_INCLUDE_FPREGS make variable allows us to include or exclude FP
registers from context structure, in case FP is not used by TSPD.
Fixes ARM-software/tf-issues#194
Change-Id: Iee41af382d691340c7ae21830ad1bbf95dad1f4b
Juan Castillo
committed
on 10 Jul 2014
|
2014-07-09 |
Refactor fvp gic code to be a generic driver
...
Refactor the FVP gic code in plat/fvp/fvp_gic.c to be a generic ARM
GIC driver in drivers/arm/gic/arm_gic.c. Provide the platform
specific inputs in the arm_gic_setup() function so that the driver
has no explicit dependency on platform code.
Provide weak implementations of the platform interrupt controller
API in a new file, plat/common/plat_gic.c. These simply call through
to the ARM GIC driver.
Move the only remaining FVP GIC function, fvp_gic_init() to
plat/fvp/aarch64/fvp_common.c and remove plat/fvp/fvp_gic.c
Fixes ARM-software/tf-issues#182
Change-Id: Iea82fe095fad62dd33ba9efbddd48c57717edd21
Dan Handley
committed
on 9 Jul 2014
|
Refactor fvp_config into common platform header
...
Changed the fvp_config array in fvp_common.c into a struct and
moved into a new optional common platform header,
include/plat/common/plat_config.h. Removed the config definitions
in fvp_def.h and updated all references to the platform config.
This makes the interface to the platform config cleaner and uses
a little less RAM.
Fixes ARM-software/tf-issues#180
Change-Id: I58dd7b3c150f24f7ee230a26fd57c827853ba803
Dan Handley
committed
on 9 Jul 2014
|
Calculate TCR bits based on VA and PA
...
Currently the TCR bits are hardcoded in xlat_tables.c. In order to
map higher physical address into low virtual address, the TCR bits
need to be configured accordingly.
This patch is to save the max VA and PA and calculate the TCR.PS/IPS
and t0sz bits in init_xlat_tables function.
Change-Id: Ia7a58e5372b20200153057d457f4be5ddbb7dae4
Lin Ma
authored
on 27 Jun 2014
Dan Handley
committed
on 9 Jul 2014
|
2014-07-01 |
Remove concept of top/bottom image loading
...
This concept is no longer required since we now support loading of
images at fixed addresses only.
The image loader now automatically detects the position of the image
inside the current memory layout and updates the layout such that
memory fragmentation is minimised.
The 'attr' field of the meminfo data structure, which used to hold
the bottom/top loading information, has been removed. Also the 'next'
field has been removed as it wasn't used anywhere.
The 'init_bl2_mem_layout()' function has been moved out of common
code and put in BL1-specific code. It has also been renamed into
'bl1_init_bl2_mem_layout'.
Fixes ARM-software/tf-issues#109
Change-Id: I3f54642ce7b763d5ee3b047ad0ab59eabbcf916d
Sandrine Bailleux
committed
on 1 Jul 2014
|
2014-06-26 |
Merge pull request #154 from athoelke/at/inline-mmio
...
Inline the mmio accessor functions
Andrew Thoelke
committed
on 26 Jun 2014
|
2014-06-24 |
Merge pull request #152 from jcastillo-arm/jc/tf-issues/073-v2
...
Remove all checkpatch errors from codebase
danh-arm
committed
on 24 Jun 2014
|
Merge pull request #147 from athoelke/at/remove-bakery-mpidr
...
Remove calling CPU mpidr from bakery lock API
danh-arm
committed
on 24 Jun 2014
|
Inline the mmio accessor functions
...
Making the simple mmio_read_*() and mmio_write_*() functions inline
saves 360 bytes of code in FVP release build.
Fixes ARM-software/tf-issues#210
Change-Id: I65134f9069f3b2d8821d882daaa5fdfe16355e2f
Andrew Thoelke
committed
on 24 Jun 2014
|
Remove all checkpatch errors from codebase
...
Exclude stdlib files because they do not follow kernel code style.
Fixes ARM-software/tf-issues#73
Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
Juan Castillo
committed
on 24 Jun 2014
|
2014-06-23 |
Remove calling CPU mpidr from bakery lock API
...
The bakery lock code currently expects the calling code to pass
the MPIDR_EL1 of the current CPU.
This is not always done correctly. Also the change to provide
inline access to system registers makes it more efficient for the
bakery lock code to obtain the MPIDR_EL1 directly.
This change removes the mpidr parameter from the bakery lock
interface, and results in a code reduction of 160 bytes for the
ARM FVP port.
Fixes ARM-software/tf-issues#213
Change-Id: I7ec7bd117bcc9794a0d948990fcf3336a367d543
Andrew Thoelke
committed
on 23 Jun 2014
|
Correctly dimension the PSCI aff_map_node array
...
The array of affinity nodes is currently allocated for 32 entries
with the PSCI_NUM_AFFS value defined in psci.h. This is not enough
for large systems, and will substantially over allocate the array
for small systems.
This patch introduces an optional platform definition
PLATFORM_NUM_AFFS to platform_def.h. If defined this value is
used for PSCI_NUM_AFFS, otherwise a value of two times the number
of CPU cores is used.
The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves
nearly 1.5KB of memory.
Fixes ARM-software/tf-issues#192
Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
Andrew Thoelke
committed
on 23 Jun 2014
|
Initialise CPU contexts from entry_point_info
...
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
* The first uses entry_point_info to initialize the relevant
cpu_context for first entry into a lower exception level on a CPU
* The second populates the EL1 and EL2 system registers as needed
from the cpu_context to ensure correct entry into the lower EL
This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).
In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.
Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
Andrew Thoelke
committed
on 23 Jun 2014
|
Merge pull request #138 from athoelke/at/cpu-context
...
Move CPU context pointers into cpu_data
danh-arm
committed
on 23 Jun 2014
|
2014-06-17 |
Remove early_exceptions from BL3-1
...
The crash reporting support and early initialisation of the
cpu_data allow the runtime_exception vectors to be used from
the start in BL3-1, removing the need for the additional
early_exception vectors and 2KB of code from BL3-1.
Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
Andrew Thoelke
committed
on 17 Jun 2014
|
2014-06-16 |
Move CPU context pointers into cpu_data
...
Moving the context pointers for each CPU into the per-cpu data
allows for much more efficient access to the contexts for the
current CPU.
Change-Id: Id784e210d63cbdcddb44ac1591617ce668dbc29f
Andrew Thoelke
committed
on 16 Jun 2014
|
Per-cpu data cache restructuring
...
This patch prepares the per-cpu pointer cache for wider use by:
* renaming the structure to cpu_data and placing in new header
* providing accessors for this CPU, or other CPUs
* splitting the initialization of the TPIDR pointer from the
initialization of the cpu_data content
* moving the crash stack initialization to a crash stack function
* setting the TPIDR pointer very early during boot
Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3
Andrew Thoelke
committed
on 16 Jun 2014
|
Merge pull request #131 from athoelke/at/cm_get_context
...
Provide cm_get/set_context() for current CPU
danh-arm
committed
on 16 Jun 2014
|
Merge pull request #130 from athoelke/at/inline-asm-sysreg-v2
...
Make system register functions inline assembly v2
danh-arm
committed
on 16 Jun 2014
|