2014-06-23 |
Correctly dimension the PSCI aff_map_node array
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The array of affinity nodes is currently allocated for 32 entries
with the PSCI_NUM_AFFS value defined in psci.h. This is not enough
for large systems, and will substantially over allocate the array
for small systems.
This patch introduces an optional platform definition
PLATFORM_NUM_AFFS to platform_def.h. If defined this value is
used for PSCI_NUM_AFFS, otherwise a value of two times the number
of CPU cores is used.
The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves
nearly 1.5KB of memory.
Fixes ARM-software/tf-issues#192
Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
Andrew Thoelke
committed
on 23 Jun 2014
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Merge pull request #143 from athoelke/at/remove-nsram
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Remove NSRAM from FVP memory map
danh-arm
committed
on 23 Jun 2014
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2014-06-20 |
Remove NSRAM from FVP memory map
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This memory is not used by the FVP port and requires an additional
4KB translation table.
This patch removes the entry from the memory map and reduces the
number of allocated translation tables.
Fixes ARM-software/tf-issues#196
Change-Id: I5b959e4fe92f5f892ed127c40dbe6c85eed3ed72
Andrew Thoelke
committed
on 20 Jun 2014
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2014-06-18 |
Merge pull request #135 from soby-mathew/sm/remove-reinit-of-timers
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Remove re-initialisation of system timers after warm boot for FVP
danh-arm
committed
on 18 Jun 2014
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Remove re-initialisation of system timers after warm boot for FVP
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This patch removes the reinitialisation of memory mapped system timer
registers after a warm boot for the FVP. The system timers in FVP are
in the 'Always ON' power domain which meant the reinitialisation was
redundant and it could have conflicted with the setup the normal
world has done.
The programming of CNTACR(x) and CNTNSAR, the system timer registers,
are removed from the warm boot path with this patch.
Fixes ARM-software/tf-issues#169
Change-Id: Ie982eb03d1836b15ef3cf1568de2ea68a08b443e
Soby Mathew
committed
on 18 Jun 2014
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2014-06-17 |
Merge pull request #134 from jcastillo-arm/jc/tf-issues/179
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Set correct value for SYS_ID_REV_SHIFT in FVP
danh-arm
committed
on 17 Jun 2014
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2014-06-16 |
Set correct value for SYS_ID_REV_SHIFT in FVP
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According to documentation, the Rev field is located at bit 28 in
the V2M sysid register.
Fixes ARM-software/tf-issues#179
Change-Id: I2abb7bdc092ccd3f41f8962dc8d8d8e44e8dfdc3
Juan Castillo
committed
on 16 Jun 2014
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Merge pull request #130 from athoelke/at/inline-asm-sysreg-v2
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Make system register functions inline assembly v2
danh-arm
committed
on 16 Jun 2014
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2014-06-12 |
Merge pull request #125 from sandrine-bailleux/sb/remove-bl2_el_change_mem_ptr
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fvp: Remove unused 'bl2_el_change_mem_ptr' variable
achingupta
committed
on 12 Jun 2014
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2014-06-10 |
Make system register functions inline assembly
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Replace the current out-of-line assembler implementations of
the system register and system instruction operations with
inline assembler.
This enables better compiler optimisation and code generation
when accessing system registers.
Fixes ARM-software/tf-issues#91
Change-Id: I149af3a94e1e5e5140a3e44b9abfc37ba2324476
Andrew Thoelke
committed
on 10 Jun 2014
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2014-06-05 |
fvp: Remove unused 'bl2_el_change_mem_ptr' variable
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'bl2_el_change_mem_ptr' variable is a left over from the former
BL2/BL3-1 interface.
Change-Id: Ib0979c8e2809e103a41f9c5cc4afec7dd21ac9ab
Sandrine Bailleux
committed
on 5 Jun 2014
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2014-06-02 |
Enable mapping higher physical address
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Current ATF uses a direct physical-to-virtual mapping, that is, a physical
address is mapped to the same address in the virtual space. For example,
physical address 0x8000_0000 is mapped to 0x8000_0000 virtual. This
approach works fine for FVP as all its physical addresses fall into 0 to
4GB range. But for other platform where all I/O addresses are 48-bit long,
If we follow the same direct mapping, we would need virtual address range
from 0 to 0x8fff_ffff_ffff, which is about 144TB. This requires a
significant amount of memory for MMU tables and it is not necessary to use
that much virtual space in ATF.
The patch is to enable mapping a physical address range to an arbitrary
virtual address range (instead of flat mapping)
Changed "base" to "base_va" and added "base_pa" in mmap_region_t and
modified functions such as mmap_add_region and init_xlation_table etc.
Fixes ARM-software/tf-issues#158
Lin Ma
committed
on 2 Jun 2014
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2014-05-29 |
Allow platform parameter X1 to be passed to BL3-1
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bl2_main() was overwriting any platform set X1 parameter for BL3-1
with the value zero.
This patch ensure that any platform set value is correctly passed
to BL3-1. The FVP port adds a check to verify this parameter is
being passed correctly.
Fixes ARM-software/tf-issues#173
Change-Id: Ifbcda73d3d41d2b04a4baf5614e9d2d21f1717c8
Andrew Thoelke
committed
on 29 May 2014
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2014-05-27 |
Further renames of platform porting functions
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Rename the ic_* platform porting functions to plat_ic_* to be
consistent with the other functions in platform.h. Also rename
bl31_get_next_image_info() to bl31_plat_get_next_image_ep_info()
and remove the duplicate declaration in bl31.h.
Change-Id: I4851842069d3cff14c0a468daacc0a891a7ede84
Dan Handley
committed
on 27 May 2014
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2014-05-23 |
Add enable mmu platform porting interfaces
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Previously, the enable_mmu_elX() functions were implicitly part of
the platform porting layer since they were included by generic
code. These functions have been placed behind 2 new platform
functions, bl31_plat_enable_mmu() and bl32_plat_enable_mmu().
These are weakly defined so that they can be optionally overridden
by platform ports.
Also, the enable_mmu_elX() functions have been moved to
lib/aarch64/xlat_tables.c for optional re-use by platform ports.
These functions are tightly coupled with the translation table
initialization code.
Fixes ARM-software/tf-issues#152
Change-Id: I0a2251ce76acfa3c27541f832a9efaa49135cc1c
Dan Handley
authored
on 16 May 2014
Achin Gupta
committed
on 23 May 2014
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Rename FVP specific files and functions
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FVP specific files and functions containing the word "plat" have been
renamed to use the word "fvp" to distinguish them from the common
platform functionality and porting functions.
Change-Id: I39f9673dab3ee9c74bd18b3e62b7c21027232f7d
Dan Handley
authored
on 15 May 2014
Achin Gupta
committed
on 23 May 2014
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Move BL porting functions into platform.h
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Some platform porting functions were in BL specific header files.
These have been moved to platform.h so that all porting functions
are in the same place. The functions are now grouped by BL.
Obsolete BL headers files have been removed.
Also, the weak declaration of the init_bl2_mem_layout() function
has been moved out the header file and into the source file
(bl_common.c) using the more succinct #pragma syntax. This
mitigates the risk of 2 weak definitions being created and the
wrong one being picked up by the compiler.
Change-Id: Ib19934939fd755f3e5a5a5bceec88da684308a83
Dan Handley
authored
on 15 May 2014
Achin Gupta
committed
on 23 May 2014
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Split platform.h into separate headers
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Previously, platform.h contained many declarations and definitions
used for different purposes. This file has been split so that:
* Platform definitions used by common code that must be defined
by the platform are now in platform_def.h. The exact include
path is exported through $PLAT_INCLUDES in the platform makefile.
* Platform definitions specific to the FVP platform are now in
/plat/fvp/fvp_def.h.
* Platform API declarations specific to the FVP platform are now
in /plat/fvp/fvp_private.h.
* The remaining platform API declarations that must be ported by
each platform are still in platform.h but this file has been
moved to /include/plat/common since this can be shared by all
platforms.
Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a
Dan Handley
authored
on 14 May 2014
Achin Gupta
committed
on 23 May 2014
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Remove unused data declarations
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Some data variables were declared but not used. These have been
removed.
Change-Id: I038632af3c32d88984cd25b886c43ff763269bf9
Dan Handley
authored
on 14 May 2014
Andrew Thoelke
committed
on 23 May 2014
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Remove extern keyword from function declarations
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Function declarations implicitly have external linkage so do not
need the extern keyword.
Change-Id: Ia0549786796d8bf5956487e8996450a0b3d79f32
Dan Handley
authored
on 14 May 2014
Andrew Thoelke
committed
on 23 May 2014
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Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2
Andrew Thoelke
committed
on 23 May 2014
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Make the memory layout more flexible
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Currently the platform code gets to define the base address of each
boot loader image. However, the linker scripts couteract this
flexibility by enforcing a fixed overall layout of the different
images. For example, they require that the BL3-1 image sits below
the BL2 image. Choosing BL3-1 and BL2 base addresses in such a way
that it violates this constraint makes the build fail at link-time.
This patch requires the platform code to now define a limit address
for each image. The linker scripts check that the image fits within
these bounds so they don't rely anymore on the position of a given
image in regard to the others.
Fixes ARM-software/tf-issues#163
Change-Id: I8c108646825da19a6a8dfb091b613e1dd4ae133c
Sandrine Bailleux
committed
on 23 May 2014
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Make BL1 RO and RW base addresses configurable
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BL1 RO and RW base address used to be fixed, respectively to the first
address of the Trusted ROM and the first address of the Trusted RAM.
Introduce new platform defines to configure the BL1 RO and RW base
addresses.
Change-Id: If26616513a47798593a4bb845a4b0fb37c867cd6
Sandrine Bailleux
committed
on 23 May 2014
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Merge pull request #104 from athoelke:at/tsp-entrypoints-v2
Andrew Thoelke
committed
on 23 May 2014
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Merge pull request #102 from achingupta:ag/tf-issues#104-v2
Andrew Thoelke
committed
on 23 May 2014
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Merge pull request #100 from jcastillo-arm:jc/tf-issues/149-v4
Andrew Thoelke
committed
on 23 May 2014
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Limit BL3-1 read/write access to SRAM
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At present BL3-1 has access to all of the SRAM, including
regions that are mapped as read-only and non-cacheable by other
firmware images.
This patch restricts BL3-1 to only be able to read/write from
memory used for its own data sections
Change-Id: I26cda1b9ba803d91a9eacda768f3ce7032c6db94
Conflicts:
plat/fvp/bl31_plat_setup.c
Andrew Thoelke
committed
on 23 May 2014
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2014-05-22 |
Add support for synchronous FIQ handling in TSP
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This patch adds support in the TSP for handling S-EL1 interrupts
handed over by the TSPD. It includes GIC support in its platform port,
updates various statistics related to FIQ handling, exports an entry
point that the TSPD can use to hand over interrupts and defines the
handover protocol w.r.t what context is the TSP expected to preserve
and the state in which the entry point is invoked by the TSPD.
Change-Id: I93b22e5a8133400e4da366f5fc862f871038df39
Achin Gupta
committed
on 22 May 2014
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Introduce platform api to access an ARM GIC
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This patch introduces a set of functions which allow generic firmware
code e.g. the interrupt management framework to access the platform
interrupt controller. APIs for finding the type and id of the highest
pending interrupt, acknowledging and EOIing an interrupt and finding
the security state of an interrupt have been added. It is assumed that
the platform interrupt controller implements the v2.0 of the ARM GIC
architecture specification. Support for v3.0 of the specification for
managing interrupts in EL3 and the platform port will be added in the
future.
Change-Id: Ib3a01c2cf3e3ab27806930f1be79db2b29f91bcf
Achin Gupta
committed
on 22 May 2014
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Introduce interrupt registration framework in BL3-1
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This patch introduces a framework for registering interrupts routed to
EL3. The interrupt routing model is governed by the SCR_EL3.IRQ and
FIQ bits and the security state an interrupt is generated in. The
framework recognizes three type of interrupts depending upon which
exception level and security state they should be handled in
i.e. Secure EL1 interrupts, Non-secure interrupts and EL3
interrupts. It provides an API and macros that allow a runtime service
to register an handler for a type of interrupt and specify the routing
model. The framework validates the routing model and uses the context
management framework to ensure that it is applied to the SCR_EL3 prior
to entry into the target security state. It saves the handler in
internal data structures. An API is provided to retrieve the handler
when an interrupt of a particular type is asserted. Registration is
expected to be done once by the primary CPU. The same handler and
routing model is used for all CPUs.
Support for EL3 interrupts will be added to the framework in the
future. A makefile flag has been added to allow the FVP port choose
between ARM GIC v2 and v3 support in EL3. The latter version is
currently unsupported.
A framework for handling interrupts in BL3-1 will be introduced in
subsequent patches. The default routing model in the absence of any
handlers expects no interrupts to be routed to EL3.
Change-Id: Idf7c023b34fcd4800a5980f2bef85e4b5c29e649
Achin Gupta
committed
on 22 May 2014
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