2016-08-24 |
rockchip: on rk3399 init the PMU counts at boot; set 24M/32k properly
...
In a previous change we mistakenly thought that PMU_24M_EN_CFG directly
controlled whether the PMU counts ran off the 32k vs. 24M clock.
Apparently that's not true. Real logic is now documented in code.
Also in the previous change we mistaknely though that PMU_24M_EN_CFG was
normally supposed to be 1 and we should "restore" it at resume time.
This is a terrible idea and made the system totally unreliable after
resume. Apparently PMU_24M_EN_CFG should always be 0 with all the
current code and settings.
Let's fix the above two problems. While we're changing all of this,
let's also:
1. Init at boot time. Many of these counts are used when the system is
running normally. We want the behavior at boot to match the behavior
after suspend/resume.
2. Init CPU counts to be 1 us. Although old code was trying to set this
to 1 ms (1000x slower) at suspend/resume time, we've been testing the
kernel with 1 us for a long time now. That's because the kernel (at
boot time) set these values to 24. Let's keep at 24 until we know
that's wrong.
3. Init GPU counts to be 1 us. Old code wasn't touching the GPU, but as
documented in comments it makes sense to init here. Do it.
4. Document the crap out of this code, since the SoC's behavior is
confusing and poorly documented in the TRM.
5. Increase some stabilization times to 30 ms (from 3 ms). It's unclear
that a full 30 ms is needed, but let's be safe for now.
This also inits the counts for the GPU.
(Thanks to Doug's patch that come from https://crosreview.com/372381)
Change-Id: Id1bc159a5a99916aeab043895e5c4585c4adab22
Caesar Wang
committed
on 24 Aug 2016
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2016-08-23 |
Automatically select initial xlation lookup level
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Instead of hardcoding a level 1 table as the base translation level
table, let the code decide which level is the most appropriate given
the virtual address space size.
As the table granularity is 4 KB, this allows the code to select
level 0, 1 or 2 as base level for AArch64. This way, instead of
limiting the virtual address space width to 39-31 bits, widths of
48-25 bit can be used.
For AArch32, this change allows the code to select level 1 or 2
as the base translation level table and use virtual address space
width of 32-25 bits.
Also removed some unused definitions related to translation tables.
Fixes ARM-software/tf-issues#362
Change-Id: Ie3bb5d6d1a4730a26700b09827c79f37ca3cdb65
Antonio Nino Diaz
authored
on 2 Aug 2016
Soby Mathew
committed
on 23 Aug 2016
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2016-08-22 |
Remove looping around `plat_report_exception`
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This patch removes the tight loop that calls `plat_report_exception`
in unhandled exceptions in AArch64 state.
The new behaviour is to call the `plat_report_exception` only
once followed by call to `plat_panic_handler`.
This allows platforms to take platform-specific action when
there is an unhandled exception, instead of always spinning
in a tight loop.
Note: This is a subtle break in behaviour for platforms that
expect `plat_report_exception` to be continuously executed
when there is an unhandled exception.
Change-Id: Ie2453804b9b7caf9b010ee73e1a90eeb8384e4e8
Yatharth Kochar
committed
on 22 Aug 2016
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2016-08-19 |
Merge pull request #687 from sandrine-bailleux-arm/sb/panic-handler
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Add WFI in platform's unexpected error handlers
danh-arm
authored
on 19 Aug 2016
GitHub
committed
on 19 Aug 2016
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Add WFI in platform's unexpected error handlers
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This patch adds a WFI instruction in the default implementations of
plat_error_handler() and plat_panic_handler(). This potentially reduces
power consumption by allowing the hardware to enter a low-power state.
The same change has been made to the FVP and Juno platform ports.
Change-Id: Ia4e6e1e5bf1ed42efbba7d0ebbad7be8d5f9f173
Sandrine Bailleux
committed
on 19 Aug 2016
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2016-08-18 |
Merge pull request #686 from danh-arm/dh/remove-inv-dcache-after-auth
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Remove dcache invalidation after image authentication
danh-arm
authored
on 18 Aug 2016
GitHub
committed
on 18 Aug 2016
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Merge pull request #678 from soby-mathew/sm/PSCI_AArch32
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Introduce AArch32 support for PSCI library
danh-arm
authored
on 18 Aug 2016
GitHub
committed
on 18 Aug 2016
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2016-08-17 |
Remove dcache invalidation after image authentication
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At the end of successful image authentication in load_auth_image(),
the data cache for the virtual address range corresponding to the
image is invalidated (by a call to inv_dcache_range()). The intent
seems to be to ensure the data caches do not contain any sensitive
data used during authentication, which subsequent code can read.
However, this same address range is already flushed (cleaned and
invalidated by a call to flush_dcache_range()) at the end of
load_image(), and the subsequent invalidate has no functional
effect.
This patch removes the redundant call to inv_dcache_range(). It
also moves the flush_dcache_range() call from the end of load_image()
to the end of load_auth_image(), so the image data will remain in
the caches during authentication, improving performance.
This also improves the comments that explain the rationale for
calling flush_dcache_range() after image loading/authentication.
Change-Id: I14f17ad2935075ef6f3d1327361c5088bfb2d284
Dan Handley
committed
on 17 Aug 2016
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Merge pull request #685 from sandrine-bailleux-arm/sb/base-fvp-7.6
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Move up to Base FVP version 7.6
danh-arm
authored
on 17 Aug 2016
GitHub
committed
on 17 Aug 2016
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Merge pull request #683 from dp-arm/dp/fiptool
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fiptool: Suppress verbose messages during normal build
danh-arm
authored
on 17 Aug 2016
GitHub
committed
on 17 Aug 2016
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Merge pull request #682 from sudeep-holla/gicv3_ns_intr
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gicv3: disable Group1 NonSecure interrupts during core powerdown
danh-arm
authored
on 17 Aug 2016
GitHub
committed
on 17 Aug 2016
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Merge pull request #680 from hzhuang1/emmc_cmd23_v2
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emmc: support CMD23
danh-arm
authored
on 17 Aug 2016
GitHub
committed
on 17 Aug 2016
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2016-08-16 |
Move up to Base FVP version 7.6
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This patch updates the User Guide to move up from version 7.2 to 7.6
of the Base FVP.
Change-Id: I792b2250deb4836266e14b40992ae59a5ab5f729
Sandrine Bailleux
committed
on 16 Aug 2016
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2016-08-15 |
fiptool: Suppress verbose messages during normal build
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The output is shown only when built with V=1.
Change-Id: I17fef10df6f127f07956a78b478ff3cadba4bd61
dp-arm
committed
on 15 Aug 2016
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AArch32: Enable build at top level Makefile for FVP
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This patch enables the AArch32 build including SP_MIN in the
top level Makefile. The build flag `ARCH` now can specify either
`aarch64`(default) or `aarch32`. Currently only FVP AEM model is
supported for AArch32 build. Another new build flag `AARCH32_SP`
is introduced to specify the AArch32 secure payload to be built.
Change-Id: Ie1198cb9e52d7da1b79b93243338fc3868b08faa
Soby Mathew
committed
on 15 Aug 2016
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2016-08-12 |
Merge pull request #679 from rockchip-linux/support-pwm-for-rk3399
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Support pwm for rk3399
danh-arm
authored
on 12 Aug 2016
GitHub
committed
on 12 Aug 2016
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2016-08-11 |
emmc: support CMD23
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Support CMD23. When CMD23 is used, CMD12 could be avoided.
Two scenarios:
1. CMD17 for single block, CMD18 + CMD12 for multiple blocks.
2. CMD23 + CMD18 for both single block and multiple blocks.
The emmc_init() should initialize whether CMD23 is supported
or not.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 11 Aug 2016
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gicv3: disable Group1 NonSecure interrupts during core powerdown
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As per the GICv3 specification, to power down a processor using GICv3
and allow automatic power-on if an interrupt must be sent to a processor,
software must set Enable to zero for all interrupt groups(by writing to
GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.
Also, NonSecure EL1 software may not be aware of the CPU power state
details and fail to choose right states that require quiescing the CPU
interface. So it's preferred that the PSCI implementation handles it as
it is fully aware of the CPU power states.
This patch adds disabling of Group1 NonSecure interrupts during processor
power down along with Group0 and Group1 Secure interrupts so that all the
interrupt groups are handled at once as per specification.
Change-Id: Ib564d773c9c4c41f2ca9471451c030e3de75e641
Sudeep Holla
committed
on 11 Aug 2016
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rockchip: fix the reset-hold release for rk3399 resume
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The pmusgrf reset-hold bits needs to be released, since the
pmusgrf reset-hold bits needs to be held.
Change-Id: Ia1eccc8fba18294f26b4cc07d47bc5e513dd9a1f
Caesar Wang
committed
on 11 Aug 2016
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rockchip: fix the power up/dowm cnt for rk3399
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Sometimes this will cause the long delay for suspend/resume.
Since the 24M OCS will be turned off in power mode.
Also, remove the ERROR_DEPRECATED config define.
Change-Id: I78f21c35912c2250972e551695cdacc7bc4c020a
Caesar Wang
committed
on 11 Aug 2016
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rockchip: update to handle PWMs for rk3399
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This patch updates some things for rk3399, as following:
1) Add the new file to handle the pwm. (e.g. the pwm regulator)
Make sure that good deal with the pwm related things.
Also, remove some pwm setting for pmu.c.
2) Set the plls slow mode and bypass in suspend, and restore them.
Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264
Caesar Wang
committed
on 11 Aug 2016
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2016-08-10 |
AArch32: Add FVP support for SP_MIN
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This patch implements the support for SP_MIN in FVP. The SP_MIN platform
APIs are implemented and the required makefile support is added for FVP.
Change-Id: Id50bd6093eccbd5e38894e3fd2b20d5baeac5452
Soby Mathew
committed
on 10 Aug 2016
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AArch32: Add essential ARM platform and FVP support
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This patch adds AArch32 support for FVP and implements common platform APIs
like `plat_get_my_stack`, `plat_set_my_stack`, `plat_my_core_cos` for AArch32.
Only Multi Processor(MP) implementations of these functions are considered in
this patch. The ARM Standard platform layer helpers are implemented for
AArch32 and the common makefiles are modified to cater for both AArch64 and
AArch32 builds. Compatibility with the deprecated platform API is not
supported for AArch32.
Change-Id: Iad228400613eec91abf731b49e21a15bcf2833ea
Soby Mathew
committed
on 10 Aug 2016
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AArch32: add a minimal secure payload (SP_MIN)
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This patch adds a minimal AArch32 secure payload SP_MIN. It relies on PSCI
library to initialize the normal world context. It runs in Monitor mode
and uses the runtime service framework to handle SMCs. It is added as
a BL32 component in the Trusted Firmware source tree.
Change-Id: Icc04fa6b242025a769c1f6c7022fde19459c43e9
Soby Mathew
committed
on 10 Aug 2016
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AArch32: Add support to PSCI lib
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This patch adds AArch32 support to PSCI library, as follows :
* The `psci_helpers.S` is implemented for AArch32.
* AArch32 version of internal helper function `psci_get_ns_ep_info()` is
defined.
* The PSCI Library is responsible for the Non Secure context initialization.
Hence a library interface `psci_prepare_next_non_secure_ctx()` is introduced
to enable EL3 runtime firmware to initialize the non secure context without
invoking context management library APIs.
Change-Id: I25595b0cc2dbfdf39dbf7c589b875cba33317b9d
Soby Mathew
committed
on 10 Aug 2016
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AArch32: Add support in TF libraries
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This patch adds AArch32 support to cpu ops, context management,
per-cpu data and spinlock libraries. The `entrypoint_info`
structure is modified to add support for AArch32 register
arguments. The CPU operations for AEM generic cpu in AArch32
mode is also added.
Change-Id: I1e52e79f498661d8f31f1e7b3a29e222bc7a4483
Soby Mathew
committed
on 10 Aug 2016
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AArch32: Add console driver
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This patch adds console drivers including the pl011 driver
for the AArch32 mode.
Change-Id: Ifd22520d370fca3e73dbbf6f2d97d6aee65b67dd
Soby Mathew
committed
on 10 Aug 2016
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AArch32: Enable GIC and TZC support
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This patch modifies GICv3 and TZC drivers to add AArch32 support.
No modifications are required for the GICv2 driver for AArch32 support.
The TZC driver assumes that the secure world is running in Little-Endian
mode to do 64 bit manipulations. Assertions are present to validate the
assumption.
Note: The legacy GICv3 driver is not supported for AArch32.
Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458
Soby Mathew
committed
on 10 Aug 2016
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AArch32: Add SMCC context
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This patch defines a SMCC context to save and restore
registers during a SMC call. It also adds appropriate helpers
to save and restore from this context for use by AArch32
secure payload and BL stages.
Change-Id: I64c8d6fe1d6cac22e1f1f39ea1b54ee1b1b72248
Soby Mathew
committed
on 10 Aug 2016
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AArch32: Add API to invoke runtime service handler
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This patch adds an API in runtime service framework to
invoke the registered handler corresponding to the SMC function
identifier. This is helpful for AArch32 because the number of
arguments required by the handler is more than registers
available as per AArch32 program calling conventions and
requires the use of stack. Hence this new API will do the
necessary argument setup and invoke the appropriate
handler. Although this API is primarily intended for AArch32,
it can be used for AArch64 as well.
Change-Id: Iefa15947fe5a1df55b0859886e677446a0fd7241
Soby Mathew
committed
on 10 Aug 2016
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