Tegra: dummy support for the io_storage backend ...

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: Support for scatterfile for the BL31 image ...

This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable the scatterfile usage the following changes
have been made:

* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
  to compile BL31
* update pubsub.h to add sections to the scatterfile

NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.

Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: trampoline: include bl_common.h ...

This patch includes bl_common.h from plat_trampoline.S to link with
the __BL31_END__ symbol.

Change-Id: Ie66c5009018472607db668583c9a0b3553f0ae73
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: use common 'BL31_BASE' variable ...

This patch modfies the 'tegra_soc_pwr_domain_power_down_wfi' handler
to use BL31_BASE variable, provided by bl_common.h

Change-Id: I9747228d0193c1ae6999284458b9f866955a61a2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: remove circular dependency with common_def.h ...

This patch stops including common_def.h from platform_def.h to
fix a circular depoendency between them.

This means platform_def.h now has to define the linker macros:
* PLATFORM_LINKER_FORMAT
* PLATFORM_LINKER_ARCH

Change-Id: Icd540b1bd32fb37e0e455e9146c8b7f4b314e012
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: define CACHE_WRITEBACK_GRANULE for scatterfile ...

The scatterfile to support armlink, does not seem to support
shift operator. To handle this define CACHE_WRITEBACK_GRANULE with
the direct value.

Change-Id: I19afc7cb9c55a08cb0703f284d91018d3214353f
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

Tegra186: remove ENABLE_AFI_DEVICE macro usage ...

This patch removes this macro and its usage as it is used only
within the Tegra186 files and all derived platforms keep the
macro enabled.

Change-Id: Ib831b3c002ba4dedc3d5fafbb7d321daa28fa9ea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

spd: trusty: memmap trusty's code memory before peeking ...

This patch dynamically maps the first page of trusty's code memory,
before accessing it to find out if we are running a 32-bit or 64-bit
image.

On Tegra platforms, this means we have to increase the mappings to
accomodate the new memmap entry.

Change-Id: If370d1e6cfcccd69b260134c1b462d8d17bee03d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: initialise per-CPU GIC interface(s) ...

This patch initilises the per-CPU GIC bits during cold boot and
secondary CPU power up. Commit 80c50ee accidentally left out this
part.

Change-Id: I73ce59dbc83580a84b827cab89fe7e1f65f9f130
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: spe: prepend '\r' to '\n' ...

This patch udpates the SPE console driver to prepend '\r' to
'\n'. This fixes the alignment of prints seen by the host
machines on their UART ports.

Tested by collecting the logs from host PC using Cutecom

Reported by: Mustafa Bilgen <mbilgen@nvidia.com>

Change-Id: I6e0b412bd71ff5eb889582071df8c157da5175ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: Enable irq as wake-up event for cpu_standby ...

As per ARM ARM D1.17.2, any physical IRQ interrupt received by the PE
will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
irrespective of the value of the PSTATE.I bit value.

This patch programs the SCR_EL3.IRQ bit before entering CPU standby
state, to allow an IRQ to wake the PE. On waking up, the previous
SCR_EL3 value is restored.

Change-Id: Ie81cf3a7668f5ac35f4bf2ecc461b91b9b60650c
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

Tegra: remove unused libc files from makefile ...

This patch redefines the variable LIBC_SRCS for Tegra platforms,
to remove unused libc files from the list. This patch is a building
block to eventually use other libc implementations in the future.

Change-Id: Iccde5a75f5e2d6f4e2dbc6274beb423b80e846fd
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: restrict non-secure PMC accesses ...

Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always access the PMC through the EL3
exception space.

This patch restricts non-secure world access to the PMC block on
such platforms.

Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: memctrl: disable stream id writes for MC clients ...

As per the latest recommendations from the hardware team, write access
needs to be disabled for APE, BPMP, NvDec and SCE clients. This patch
disables stream id register writes for these MC clients to implement
those recommendations.

Change-Id: I8887c0f2cc5bc3fc5bba42074810ba5c1d3f121f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

Tegra: bpmp: mark device "not present" on boot timeout ...

This patch updates the state machine to "not present" if the bpmp
firmware is not found in the system during boot. The suspend
handler also checks now if the interface exists, before updating
the internal state machine.

Reported by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

Change-Id: If8fd7f8e412bb603944555c24826855226e7f48c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: toggle ring oscillator across cluster idle ...

This patch toggles the ring oscillator state across cluster idle
as DFLL loses its state. We dont want garbage values being written
to the pmic when we enter cluster idle state, so enable "open loop"
when we enter CC6 and restore the state to "closed loop" on exit.

Change-Id: I56f4649f57bcc651d6c415a6dcdc978e9444c97b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: clear PMC_DPD registers on resume ...

This patch clears the PMC's DPD registers on resuming from System
Suspend, for all Tegra210 platforms that support the sc7entry-fw.

Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

Tegra210: suspend/resume bpmp interface across System Suspend ...

The BPMP firmware takes some time to initialise its state on exiting
System Suspend state. The CPU needs to synchronize with the BPMP during
this process to avoid any race conditions. This patch suspends and resumes
the BPMP interface across a System Suspend cycle, to fix this race.

Change-Id: I82a61d12ef3eee267bdd8d4386bed23397fbfd2d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: bpmp: suspend/resume handlers ...

This patch adds suspend and resume handlers for the BPMP
interface. Mark the interface as "suspended" before entering
System Suspend and verify that BPMP is alive on exit.

Change-Id: I74ccbc86125079b46d06360fc4c7e8a5acfbdfb2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: skip past sc7entry-fw signature header ...

This patch skips past the signature header added to the sc7entry-fw
binary by the previous level bootloader. Currently, the size of
the header is 1KB, so adjust the start address and the binary size
at the time of copy.

Change-Id: Id0494548009749035846d54df417a960c640c8f9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: move sc7entry-fw inside the TZDRAM fence ...

This patch uses the sc7entry-fw base/size values to calculate the
TZDRAM fence, so as to move sc7entry-fw inside the TZDRAM fence.

Change-Id: I91aeeeece857076c478cdc4c18a6ad70dc265031
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: SiP handlers to allow PMC access ...

This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.

Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

Tegra210: power off all DMA masters before System Suspend entry ...

This patch puts all the DMA masters in reset before starting the System
Suspend sequence. This helps us make sure that there are no rogue agents
in the system trying to over-write the SC7 Entry Firmware with their own.

Change-Id: I7eb39999d229951e612fbfeb9f86c4efb8f98b5a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: support for System Suspend using sc7entry-fw binary ...

This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.

The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.

The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.

To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.

Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: remove support for cluster power down ...

This patch removes support for powering down a CPU cluster on
Tegra210 platforms as none of them actually use it.

Change-Id: I9665634cf2b5b7b8a1b5a2700cae152dc9165fe3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: support for cluster idle from the CPU ...

This patch adds support to enter/exit to/from cluster idle power
state on Tegra210 platforms that do not load BPMP firmware.

The CPU initates the cluster idle sequence on the last standing
CPU, by following these steps:

Entry
-----
* stop other CPUs from waking up
* program the PWM pinmux to tristate for OVR PMIC
* program the flow controller to enter CC6 state
* skip L1 $ flush during cluster power down, as L2 $ is inclusive
  of L1 $ on Cortex-A57 CPUs

Exit
----
* program the PWM pinmux to un-tristate for OVR PMIC
* allow other CPUs to wake up

This patch also makes sure that cluster idle state entry is not
enabled until CL-DVFS is ready.

Change-Id: I54cf31bf72b4a09d9bf9d2baaed6ee5a963c7808
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: pmc: helper function to find last ON CPU ...

This patch adds a helper function to find the last standing CPU
in a cluster.

Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: platform dependent address space sizes ...

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.

Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra: organize memory/mmio apertures to decrease memmap latency ...

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been moved
to individual platforms instead of making it a common step, as it
further speeds up the memory map creation process.

Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: Enable WDT_CPU interrupt for FIQ Debugger ...

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.

Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>