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2020-12-27	0db4839 Browse files » stm32mp1: add low power management ... Change-Id: I8e0ba794e5ded1290fb83fe8d43ce54d4dc0e320 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 20 May 2019 Jookia committed on 27 Dec 2020
	fb4d5a7 Browse files » ddr: stm32mp1: add DDR self-refresh management ... In order to prepare low power use cases, functions are added to manage the entry or exit of DDR from self-refresh mode. Change-Id: I8a1cbc48d613366fca69b4fc6870e53f8b917598 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 24 Apr 2019 Jookia committed on 27 Dec 2020
	c7541b8 Browse files » stm32mp1: add RTC driver ... This driver is responsible to manage STM32MP1 Real Time Clock IP. Change-Id: I8bb84cf2a2786be718944d69153f676d57bfbc37 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Yann Gautier authored on 13 May 2019 Jookia committed on 27 Dec 2020
	107259d Browse files » aarch32: add virtual timer control support ... Define virtual timer resources for a platform to be able to control virtual timers, even if TF-A does not enable them. This is required for example when the secure world wants to reset the system. Virtual timers enabled from non-secure world can jeopardize the reset sequence due to pending interrupts. Change-Id: Ieb0ce4819809ae9c4ab11f9244a6cacf9437d6b4 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 21 May 2019 Jookia committed on 27 Dec 2020
	55d14e0 Browse files » arch: rename CNTBaseN register offsets defines ... The CNTFRQ already has a CNTBASEN_ prefix. To be able to use CNTP_CTL from CP15, the CNTP_CTL define is renamed CNTBASEN_CNTP_CTL. To keep consistency, CNTPCT_LO and CNTP_CVAL_LO are also prefixed. Change-Id: Ie328daa694a708130ee369218b57c0f4b08f7f44 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier authored on 21 May 2019 Jookia committed on 27 Dec 2020
2019-10-11	89632e6 Browse files » Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__ ... Change-Id: I497072575231730a216220f84a6d349a48eaf5e3 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Balint Dobszay committed on 11 Oct 2019
2019-10-08	9d811b8 Browse files » delay: correct timeout_init_us() ... The function has to use read_cntpct_el0() to update the counter, and not read_cntfrq_el0(). Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 8 Oct 2019
2019-10-07	80003d8 Browse files » Merge "Explicitly disable the SPME bit in MDCR_EL3" into integration Soby Mathew authored on 7 Oct 2019 TrustedFirmware Code Review committed on 7 Oct 2019
	25792ce Browse files » Merge "Neoverse N1 Errata Workaround 1542419" into integration Soby Mathew authored on 7 Oct 2019 TrustedFirmware Code Review committed on 7 Oct 2019
	2a7adf2 Browse files » Explicitly disable the SPME bit in MDCR_EL3 ... Currently the MDCR_EL3 initialisation implicitly disables MDCR_EL3.SPME by using mov_imm. This patch makes the SPME bit more visible by explicitly disabling it and documenting its use in different versions of the architecture. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3 Petre-Ionut Tudor committed on 7 Oct 2019
2019-10-04	8094262 Browse files » Neoverse N1 Errata Workaround 1542419 ... Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6 laurenw-arm authored on 20 Aug 2019 Deepika Bhavnani committed on 4 Oct 2019
2019-10-03	0711ee5 Browse files » delay: timeout detection support ... Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c Lionel Debieve committed on 3 Oct 2019
	78f02ae Browse files » Introducing support for Cortex-A65AE ... Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis <imre.kis@arm.com> Imre Kis committed on 3 Oct 2019
	2d35bc1 Browse files » Merge changes from topic "stm32mp_corrections_w40" into integration ... * changes: gpio: stm32_gpio: do not mix error code types fdts: stm32mp1: move FDCAN to PLL4_R mmc: increase delay between ACMD41 retries crypto: stm32_hash: align stm32_hash_update() prototype Soby Mathew authored on 3 Oct 2019 TrustedFirmware Code Review committed on 3 Oct 2019
	34c4f86 Browse files » Merge "Add missing support for BL2_AT_EL3 in XIP memory" into integration Soby Mathew authored on 3 Oct 2019 TrustedFirmware Code Review committed on 3 Oct 2019
	19e2af7 Browse files » crypto: stm32_hash: align stm32_hash_update() prototype ... Use size_t for length parameter in header file, as in .c file. Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 3 Oct 2019
2019-10-02	6ad216d Browse files » Introducing support for Cortex-A65 ... Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis <imre.kis@arm.com> Imre Kis committed on 2 Oct 2019
2019-10-02	0a12302 Browse files » Add missing support for BL2_AT_EL3 in XIP memory ... Add the missing flag for aarch32 XIP memory mode. It was previously added in aarch64 only. Minor: Correct the aarch64 missing flag. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iac0a7581a1fd580aececa75f97deb894858f776f Lionel Debieve committed on 2 Oct 2019
2019-10-01	3bdade5 Browse files » Merge "Cortex_hercules: Add support for Hercules-AE" into integration Soby Mathew authored on 1 Oct 2019 TrustedFirmware Code Review committed on 1 Oct 2019
2019-09-30	a4668c3 Browse files » Cortex_hercules: Add support for Hercules-AE ... Not tested on FVP Model. Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Artsem Artsemenka committed on 30 Sep 2019
2019-09-27	c5235ca Browse files » Merge "AArch32: Disable Secure Cycle Counter" into integration Soby Mathew authored on 27 Sep 2019 TrustedFirmware Code Review committed on 27 Sep 2019
	ace2368 Browse files » Merge changes from topic "ld/stm32-authentication" into integration ... * changes: stm32mp1: add authentication support for stm32image bsec: move bsec_mode_is_closed_device() service to platform crypto: stm32_hash: Add HASH driver Soby Mathew authored on 27 Sep 2019 TrustedFirmware Code Review committed on 27 Sep 2019
	41bda86 Browse files » Merge changes from topic "mp/giv3-discovery" into integration ... * changes: Migrate ARM platforms to use the new GICv3 API Adding new optional PSCI hook pwr_domain_on_finish_late GICv3: Enable multi socket GIC redistributor frame discovery Soby Mathew authored on 27 Sep 2019 TrustedFirmware Code Review committed on 27 Sep 2019
2019-09-26	c3e8b0b Browse files » AArch32: Disable Secure Cycle Counter ... This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov authored on 20 Aug 2019 Paul Beesley committed on 26 Sep 2019
2019-09-26	69ef7b7 Browse files » Merge changes I0283fc2e,Ib476d024,Iada05f7c into integration ... * changes: hikey: fix to load FIP by partition table. hikey960: fix to load FIP by partition table drivers: partition: support different block size Paul Beesley authored on 26 Sep 2019 TrustedFirmware Code Review committed on 26 Sep 2019
2019-09-25	6806cd2 Browse files » Migrate ARM platforms to use the new GICv3 API ... This patch invokes the new function gicv3_rdistif_probe() in the ARM platform specific gicv3 driver. Since this API modifies the shared GIC related data structure, it must be invoked coherently by using the platform specific pwr_domain_on_finish_late hook. Change-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 25 Sep 2019
	1010770 Browse files » Adding new optional PSCI hook pwr_domain_on_finish_late ... This PSCI hook is similar to pwr_domain_on_finish but is guaranteed to be invoked with the respective core and cluster are participating in coherency. This will be necessary to safely invoke the new GICv3 API which modifies shared GIC data structures concurrently. Change-Id: I8e54f05c9d4ef5712184c9c18ba45ac97a29eb7a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 25 Sep 2019
	ec83492 Browse files » GICv3: Enable multi socket GIC redistributor frame discovery ... This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 25 Sep 2019
2019-09-20	f700423 Browse files » bsec: move bsec_mode_is_closed_device() service to platform ... This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9 Lionel Debieve committed on 20 Sep 2019
2019-09-20	b1e0b11 Browse files » crypto: stm32_hash: Add HASH driver ... The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585 Lionel Debieve committed on 20 Sep 2019