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2020-11-17	0bd1a2e Browse files » docs: Update changelog for v2.4 release ... Change-Id: I67c9db2fc6d4b83fec2d001745b9305102d4a2ae Signed-off-by: Chris Kay <chris.kay@arm.com> Chris Kay authored on 29 Oct 2020 Chris Kay committed on 17 Nov 2020
2020-10-23	95fca11 Browse files » Merge "docs: marvell: update ddr3 build instructions" into integration Varun Wadekar authored on 23 Oct 2020 TrustedFirmware Code Review committed on 23 Oct 2020
2020-10-21	c4d919e Browse files » Merge changes from topic "tc0_sel2_spmc" into integration ... * changes: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context lib: el3_runtime: Conditionally save/restore EL2 NEVE registers lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context Manish Pandey authored on 21 Oct 2020 TrustedFirmware Code Review committed on 21 Oct 2020
2020-10-20	bd260fc Browse files » Merge "docs: code review guidelines" into integration Manish Pandey authored on 20 Oct 2020 TrustedFirmware Code Review committed on 20 Oct 2020
2020-10-20	062f8aa Browse files » lib: el3_runtime: Conditionally save/restore EL2 NEVE registers ... Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020
2020-10-16	3bd1957 Browse files » docs: Remove deprecated information ... There are no references to AARCH32, AARCH64 and __ASSEMBLY__ macros in the TF-A code hence removed the deprecated information mentioning about these macros in the document. Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Manish V Badarkhe authored on 7 Oct 2020 Manish V Badarkhe committed on 16 Oct 2020
	c20bbfa Browse files » docs: Update Release information for v2.5 ... Updated tentative code freeze and release target date for v2.5 release. Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Manish V Badarkhe authored on 7 Oct 2020 Manish V Badarkhe committed on 16 Oct 2020
	f329442 Browse files » docs: Update code freeze and release target date for v2.4 ... Updated code freeze and release information date for v2.4 release. Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Manish V Badarkhe authored on 7 Oct 2020 Manish V Badarkhe committed on 16 Oct 2020
2020-10-14	dfe577a Browse files » Merge "Don't return error information from console_flush" into integration Mark Dykes authored on 14 Oct 2020 TrustedFirmware Code Review committed on 14 Oct 2020
2020-10-13	6354401 Browse files » docs: update STM32MP1 with versions details ... After introducing the new STM32MP1 SoC versions in patch [1], the document describing STM32MP1 platform is updated with the information given in the patch commit message. [1]: stm32mp1: add support for new SoC profiles Change-Id: I6d7ce1a3c29678ddac78a6685f5d5daf28c3c3a1 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 13 Oct 2020
2020-10-11	583079a Browse files » docs: marvell: update ddr3 build instructions ... Add information about 2GB variant of EspressoBin V5 and use Marvell git branches which contain required fixes for EspressoBin. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I1db510f1576f4762259ad7b0c10024b8ab434a59 Pali Rohár committed on 11 Oct 2020
2020-10-09	831b0e9 Browse files » Don't return error information from console_flush ... And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 5 Aug 2020 laurenw-arm committed on 9 Oct 2020
2020-10-07	35c7537 Browse files » Workaround for Cortex A77 erratum 1925769 ... Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9 johpow01 authored on 10 Sep 2020 John Powell committed on 7 Oct 2020
2020-10-06	3fad996 Browse files » Merge "doc: Update list of supported FVP platforms" into integration Madhukar Pappireddy authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
2020-10-06	eeb77da Browse files » Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration ... * changes: docs: marvell: update mv_ddr branch plat: marvell: armada: a3k: rename the UART images archive plat: marvell: armada: a3k: allow image load to RAM address 0 marvell: comphy: cp110: add support for USB comphy polarity invert marvell: comphy: cp110: add support for SATA comphy polarity invert marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353 drivers: marvell: mochi: Update AP incoming masters secure level plat: marvell: armada: add ccu window for workaround errata-id 3033912 plat: marvell: ap806: implement workaround for errata-id FE-4265711 Manish Pandey authored on 6 Oct 2020 TrustedFirmware Code Review committed on 6 Oct 2020
2020-10-05	f8dee97 Browse files » Merge "Workaround for Cortex A76 erratum 1868343" into integration Madhukar Pappireddy authored on 5 Oct 2020 TrustedFirmware Code Review committed on 5 Oct 2020
2020-10-05	1f19411 Browse files » docs: code review guidelines ... Document the code review process in TF-A. Specifically: * Give an overview of code review and best practices. * Give guidelines for the participants in code review. * Outline responsibilities of each type of participant. * Explain the Gerrit labels used in the review process. Change-Id: I519ca4b2859601a7b897706e310f149a0c92e390 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: David Horstmann <david.horstmann@arm.com> Sandrine Bailleux authored on 17 Aug 2020 David Horstmann committed on 5 Oct 2020
2020-10-04	5ecfd89 Browse files » Merge "doc: stm32mp1: Improve OP-TEE related documentation" into integration Madhukar Pappireddy authored on 4 Oct 2020 TrustedFirmware Code Review committed on 4 Oct 2020
2020-10-04	1d935a1 Browse files » docs: marvell: update mv_ddr branch ... Now that the BLE image sources (mv_ddr) are updated, reflect the proper branch in the Armada build howto. Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 4 Oct 2020
2020-10-03	55ff05f Browse files » Workaround for Cortex A76 erratum 1868343 ... Cortex A76 erratum 1868343 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. This workaround will have a small impact on performance. This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call. SDEN can be found here: https://documentation-service.arm.com/static/5f2bed6d60a93e65927bc8e7 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7f2f9965f495540a1f84bb7dcc28aff45d6cee5d johpow01 authored on 29 Sep 2020 Alexei Fedorov committed on 3 Oct 2020
2020-10-02	8445253 Browse files » morello: Add Morello platform documentation ... Morello platform has a SCP which brings the primary Rainier CPU out of reset which starts executing at BL31. This patch provides documentation support for Morello platform. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2 Chandni Cherukuri authored on 1 Oct 2020 chandni cherukuri committed on 2 Oct 2020
	ccf220a Browse files » doc: Update list of supported FVP platforms ... Updated the list of supported FVP platform as per latest FVP platform release. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a Manish V Badarkhe committed on 2 Oct 2020
	219e45c Browse files » doc: stm32mp1: Improve OP-TEE related documentation ... stm32mp15_optee_defconfig has been dropped from U-Boot as it became identical to stm32mp15_trusted_defconfig. Furthermore give a hint how OP-TEE is supposed to be installed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Change-Id: Id8f0bd84a87e3a62072dd4405aadddcdd3511213 Jan Kiszka committed on 2 Oct 2020
2020-10-01	ea14b51 Browse files » Crypto library: Migrate support to MbedTLS v2.24.0 ... This patch migrates the mbedcrypto dependency for TF-A to mbedTLS repo v2.24.0 which is the latest release tag. The relevant documentation is updated to reflect the use of new version. Change-Id: I116f44242e8c98e856416ea871d11abd3234dac1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 1 Oct 2020
2020-09-29	2173b3e Browse files » Merge changes from topic "fpga_generic" into integration ... * changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add devicetree file arm_fpga: Remove SPE PMU DT node if SPE is not available arm_fpga: Adjust GICR size in DT to match number of cores fdt: Add function to adjust GICv3 redistributor size drivers: arm: gicv3: Allow detecting number of cores André Przywara authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020
	c36aa3c Browse files » Merge "Workaround for Cortex A77 erratum 1508412" into integration Madhukar Pappireddy authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020
	a6c07e0 Browse files » arm_fpga: Add platform documentation ... As the Arm Ltd. FPGA port is now working for all existing images, add some documentation file. Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 29 Sep 2020
2020-09-28	dfd5bfb Browse files » plat/arm: Add platform support for Morello ... This patch adds support for Morello platform. It is an initial port which includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary bootloader. Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Signed-off-by: Anurag Koul <anurag.koul@arm.com> Chandni Cherukuri committed on 28 Sep 2020
2020-09-25	aa3efe3 Browse files » Workaround for Cortex A77 erratum 1508412 ... Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0. The workaround is a write sequence to several implementation defined registers based on A77 revision. This errata is explained in this SDEN: https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b laurenw-arm committed on 25 Sep 2020
2020-09-22	6ac269d Browse files » Select the Log Level for the Event Log Dump on Measured Boot at build time. ... Builds in Debug mode with Measured Boot enabled might run out of trusted SRAM. This patch allows to change the Log Level at which the Measured Boot driver will dump the event log, so the latter can be accessed even on Release builds if necessary, saving space on RAM. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I133689e313776cb3f231b774c26cbca4760fa120 Javier Almansa Sobrino committed on 22 Sep 2020