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History for arm-trusted-firmware / plat / intel / soc

2020-10-26	d57318b Browse files » intel: common: Fix non-MISRA compliant code v2 ... This patch is used to fix remaining non compliant code for Intel SoCFPGA's mailbox and sip driver. These changes include: - Change non-interface required uint32_t into unsigned int - Change non-negative variable to unsigned int - Remove obsolete variable initialization to 0 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	9e28590 Browse files » intel: mailbox: Fix non-MISRA compliant code ... This patch is used to fix remaining non compliant code for Intel SocFPGA's mailbox driver. These changes include: - adding integer literal for unsigned constant - fix non-boolean controlling expression - add braces even on conditional single statement bodies Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	9975604 Browse files » intel: mailbox: Mailbox error recovery handling ... Attempt to restart the mailbox if the mailbox driver not able to write any data into the mailbox command buffer. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: Ia45291c985844dec9da82839cac701347534d32b Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	d14e965 Browse files » intel: mailbox: Enable sending large mailbox command ... Allow mailbox command that is larger than mailbox command FIFO buffer size to be sent to SDM in multiple chunks. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	4978bc2 Browse files » intel: mailbox: Use retry count in mailbox poll ... Change the main loop inside mailbox poll function from while(1) to a retry counter named sdm_loop. This is to limit the maximum possible looping of the function and prevent unexpected behaviour. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	d96e7cd Browse files » intel: mailbox: Ensure time out duration is predictive ... For each count down of time out counter, wait for number of miliseconds to ensure the time out duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	6d9f9f5 Browse files » intel: mailbox: Read mailbox response even there is an error ... Mailbox driver should read the response data if the response length in the response header is non-zero even the response header indicates error (non-zero). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640 Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	39aebd3 Browse files » intel: mailbox: Driver now handles larger response ... This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	aad868b Browse files » intel: common: Change how mailbox handles job id & buffer ... This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
2020-10-23	941fc5c Browse files » intel: common: Improve readability of mailbox read response ... Rename variables to improve readability of mailbox read response and mailbox poll response flow. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	1ae7b6f Browse files » intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB ... Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by: Richard Gong <richard.gong@intel.com> Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c Richard Gong authored on 13 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	d191eb2 Browse files » intel: common: Remove urgent from mailbox async ... Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	f8e6a09 Browse files » intel: common: Improve mailbox driver readability ... Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	516f322 Browse files » intel: common: Clean up mailbox and sip header ... Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	7f56f24 Browse files » intel: clear 'PLAT_SEC_ENTRY' in early platform setup ... Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a Chee Hong Ang authored on 24 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
2020-08-19	5a32a03 Browse files » intel: platform: Include GICv2 makefile ... This patch update each Intel's platform makefiles to include GICv2 makefile instead of manually sourcing individual c files. This aligns with latest changes from commit #1322dc94f7. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib1f446a6fc578f73a9ef86f9708ddf12d7d75f48 Abdul Halim, Muhammad Hadi Asyrafi committed on 19 Aug 2020
2020-06-08	811af8b Browse files » plat: intel: Additional instruction required to enable global timer ... There are additional instruction needed to enable the global timer. This fixes the global timer initialization Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
	27cd1a4 Browse files » plat: intel: Fix CCU initialization for Agilex ... The CCU initialization loop uses the wrong units, this fixes that. This also fixes snoop filter register set bits should be used instead of overwriting the register Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia15eeeae5569b00ad84120182170d353ee221b31 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
	e734ecd Browse files » plat: intel: Add FPGAINTF configuration to when configuring pinmux ... FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
	aea772d Browse files » plat: intel: set DRVSEL and SMPLSEL for DWMMC ... DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
	fa09d54 Browse files » plat: intel: Fix clock configuration bugs ... This fixes a few issues on the Agilex clock configuration: - Set clock manager into boot mode before configuring clock - Fix wrong divisor used when calculating vcocalib - PLL sync configuration should be read and then written - Wait PLL lock after PLL sync configuration is done - Clear interrupt bits instead of set interrupt bits after configuration Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70 Tien Hock Loh authored on 11 May 2020 Manish Pandey committed on 8 Jun 2020
2020-02-28	351d358 Browse files » Merge "intel: Enable EMAC PHY in Intel FPGA platform" into integration Sandrine Bailleux authored on 28 Feb 2020 TrustedFirmware Code Review committed on 28 Feb 2020
2020-02-28	8f74c88 Browse files » Merge "intel: Fix argument type for mailbox driver" into integration Sandrine Bailleux authored on 28 Feb 2020 TrustedFirmware Code Review committed on 28 Feb 2020
2020-02-27	960896e Browse files » intel: Update RSU driver return code ... Modify RSU driver error code for backward-compatibility with Linux RSU driver Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib9e38d4017efe35d3aceeee27dce451fbd429fb5 Abdul Halim, Muhammad Hadi Asyrafi committed on 27 Feb 2020
2020-02-25	98964f0 Browse files » 16550: Use generic console_t data structure ... Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 25 Feb 2020
2020-02-25	ea9b962 Browse files » intel: Fix argument type for mailbox driver ... This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch. Revert changing argument type from uint32_t to uint64_t to fix incompatible cast issue. Fix said bug by using intermediate uint32_t array as a more appropriate solution. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I344cdabd432cf0a0389b225c934b35d12f4c631d Abdul Halim, Muhammad Hadi Asyrafi committed on 25 Feb 2020
2020-02-24	d603fd3 Browse files » intel: Enable EMAC PHY in Intel FPGA platform ... This initializes the EMAC PHY in both Stratix 10 and Agilex, without this, EMAC PHY wouldn't work correctly. Change-Id: I7e6b9e88fd9ef472884fcf648e6001fcb7549ae6 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Tien Hock, Loh authored on 2 Oct 2019 Abdul Halim, Muhammad Hadi Asyrafi committed on 24 Feb 2020
2020-02-20	eda880f Browse files » Merge "intel: Fix Coverity Scan Defects" into integration Sandrine Bailleux authored on 20 Feb 2020 TrustedFirmware Code Review committed on 20 Feb 2020
2020-02-20	a62b47b Browse files » intel: Fix Coverity Scan Defects ... Fix mailbox driver incompatible cast bug and control flow issue that was flagged by Coverity Scan. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065 Abdul Halim, Muhammad Hadi Asyrafi committed on 20 Feb 2020
2020-02-12	78fcbd6 Browse files » Merge "intel: Change boot source selection" into integration Sandrine Bailleux authored on 12 Feb 2020 TrustedFirmware Code Review committed on 12 Feb 2020