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History for arm-trusted-firmware / plat / marvell / armada / a8k

2020-10-21	b5e3d54 Browse files » plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k ... Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6 Pali Rohár committed on 21 Oct 2020
2020-10-19	0412b73 Browse files » plat: marvell: armada: Fix including plat/marvell/marvell.mk file ... Include file plat/marvell/marvell.mk for platform A3700 was included two times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and second time from common file plat/marvell/armada/common/marvell_common.mk. It caused following warning every time was make called: plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean' plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean' Change in this commit removes inclusion of plat/marvell/marvell.mk file in common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform needs this include file, add it also into a80x0 platform specific include file lat/marvell/armada/a8k/common/a8k_common.mk. Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL are already defined, but it defines MARVELL_SECURE_BOOT variable which is needed by plat/marvell/armada/a3k/common/a3700_common.mk. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa Pali Rohár committed on 19 Oct 2020
2020-10-04	ff9cfdc Browse files » marvell: comphy: cp110: add support for USB comphy polarity invert ... The polarity inversion for USB was not tested due to lack of hw design which requires it. Currently all supported boards doesn't require USB phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Enable the option for the ones that need it. Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	38f6dac Browse files » marvell: comphy: cp110: add support for SATA comphy polarity invert ... The cp110 comphy has ability to invert RX and/or TX polarity. Polarity depends on board design. Currently all supported boards doesn't require SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	6792ba1 Browse files » plat: marvell: ap806: implement workaround for errata-id FE-4265711 ... ERRATA ID: FE-4265711 - Incorrect CNTVAL reading CNTVAL reflects the global system counter value in binary format. Due to this erratum, the CNTVAL value presented to the processor may be incorrect for several clock cycles. Workaround: Override the default value of AP Register Device General control 20 [19:16] and AP Register Device General Control 21 [11:8] to the value of 0x3. Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Stefan Chulski authored on 24 Jun 2019 Marcin Wojtas committed on 4 Oct 2020
2020-08-10	8f09da4 Browse files » Merge changes from topic "release/14.0" into integration ... * changes: docs: marvell: update PHY porting layer description docs: marvell: update path in marvell documentation docs: marvell: update build instructions with CN913x plat: marvell: octeontx: add support for t9130 plat: marvell: t9130: add SVC support plat: marvell: t9130: update AVS settings plat: marvell: t9130: pass actual CP count for load_image plat: marvell: armada: a7k: add support to SVC validation mode plat: marvell: armada: add support for twin-die combined memory device Manish Pandey authored on 10 Aug 2020 TrustedFirmware Code Review committed on 10 Aug 2020
2020-08-04	29214e9 Browse files » Use abspath to dereference $BUILD_BASE ... If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8 Grant Likely authored on 30 Jul 2020 Manish Pandey committed on 4 Aug 2020
2020-07-30	12c66c6 Browse files » plat: marvell: t9130: add SVC support ... As the preparation for adding the CN913x SoC family support introduce code that enable SVC and the frequency handling specific for the AP807 North Bridge. Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3 Signed-off-by: Alex Evraev <alexev@marvell.com> Alex Evraev authored on 6 May 2019 Marcin Wojtas committed on 30 Jul 2020
	885cd82 Browse files » plat: marvell: t9130: update AVS settings ... Update AVS settings and remove unused macros. This is a preparation patch for adding CN913x SoC family support. Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 24 Jan 2019 Marcin Wojtas committed on 30 Jul 2020
	5bc3643 Browse files » plat: marvell: t9130: pass actual CP count for load_image ... Add CN913x case to bl2_plat_get_cp_count. Fix loading of cp1/2 image. This is a preparation patch for adding CN913x SoC family support. Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9 Signed-off-by: Ben Peled <bpeled@marvell.com> Ben Peled authored on 27 Mar 2019 Marcin Wojtas committed on 30 Jul 2020
	ebf307b Browse files » plat: marvell: armada: a7k: add support to SVC validation mode ... Add support for “AVS reduction” feature at this mode for 7040 Dual Cluster operation mode at CPU=1600MHz Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2 Signed-off-by: Alex Evraev <alexev@marvell.com> Alex Evraev authored on 11 Aug 2019 Marcin Wojtas committed on 30 Jul 2020
	4827068 Browse files » plat: marvell: armada: add support for twin-die combined memory device ... the twin-die combined memory device should be treated as X8 device and not as X16 one. This patch is required to re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade. Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97 Signed-off-by: Moti Buskila <motib@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Moti Buskila authored on 6 Oct 2019 Marcin Wojtas committed on 30 Jul 2020
2020-07-21	07678ff Browse files » Merge changes I0826ef8b,I9b4659a1 into integration ... * changes: plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable Manish Pandey authored on 21 Jul 2020 TrustedFirmware Code Review committed on 21 Jul 2020
2020-07-10	a5de431 Browse files » plat: marvell: armada: mcbin: squash several IO windows into one ... There is no need to open tree different IO window when there is possibility of having one covering required range. Change-Id: I9feae1fc583df1f7d97d28161cf7601f43513856 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 10 Jun 2019 Manish Pandey committed on 10 Jul 2020
	0a977b9 Browse files » plat: marvell: armada: a8k: change CCU LLC SRAM mapping ... The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 15 Apr 2019 Manish Pandey committed on 10 Jul 2020
	0eb3d1f Browse files » plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS ... Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module. It is followed by 4MB of shared memory. Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 15 Apr 2019 Manish Pandey committed on 10 Jul 2020
	9b88367 Browse files » drivers: marvell: mg_conf_cm3: add basic driver ... Implement function which will allow to start AP FW. Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 12 Apr 2019 Manish Pandey committed on 10 Jul 2020
2020-07-03	70ec0d7 Browse files » plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board ... Add support for the iEi Puzzle-M801 board that is based on the Marvell Armada 88F8040 SoC. It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC). The iEi Puzzle-M801 board is using a custom MCU to handle board power management. The MCU is managing the boards power LEDs, fans and some other periferals. It's using UART for communication. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8 Luka Kovacic authored on 4 Dec 2019 Luka Kovačič committed on 3 Jul 2020
2020-07-03	148798c Browse files » plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable ... Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for determening the path of the system_power.c file. The variable was not updated, when it was deprecated in a8k_common.mk in commit `613bbde`. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8 Luka Kovacic authored on 3 Jul 2020 Luka Kovačič committed on 3 Jul 2020
2020-06-19	47d1773 Browse files » plat: marvell: armada: a8k: add OP-TEE OS MMU tables ... Adjust the latest OP-TEE memory definitions to the newest TF-A baseline. Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 15 Apr 2019 Marcin Wojtas committed on 19 Jun 2020
	8544080 Browse files » plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms ... Extend the CCU tables with secure SRAM window in all board setups that uses SoCs based on AP806/AP807 North Bridges Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	94d6f48 Browse files » plat: marvell: armada: reduce memory size reserved for FIP image ... It is not needed to reserve 64MB for FIP. Limit this to 4MB for both supported Armada SoC families. Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Extract from bigger commit] Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 19 Jun 2020
	63a0b12 Browse files » plat: marvell: armada: platform definitions cleanup ... - Remove TRUSTED_DRAM_BASE TRUSTED_DRAM_SIZE MARVELL_TRUSTED_SRAM_BASE - Rename PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_* PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_* MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM - Move MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h - Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map - Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM - Add minor style improvents Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Improve patch after rebase] Signed-off-by: Marcin Wojtas <mw@semihalf.com> Konstantin Porotchkin authored on 19 Jun 2020 Marcin Wojtas committed on 19 Jun 2020
	c96aa7f Browse files » plat: marvell: armada: a8k: check CCU window state before loading MSS BL2 ... Make sure the current CCU window is not in use before adding a new address map during MSS BL2 image load preparations. At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is added to MSS BL2 stage initialization, the DDR entry will be destroyed and lead to the system hang. Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	e825176 Browse files » plat: marvell: a8k: move address config of cp1/2 to BL2 ... The configuration space of each standalone CP was updated in BL31. Loading FW procedure take places earlier in SCP_BL2. It needs to be done after access to each CP is provided. Moving the proper configuration from BL31 to BL2 solves it. Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea Signed-off-by: Ben Peled <bpeled@marvell.com> Ben Peled authored on 26 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	cdfbbfe Browse files » plat: marvell: armada: re-enable BL32_BASE definition ... As a preparation to support proper loading the OPTEE OS image, enable the BL32 specific defines in case the SPD is used. On the occasion move two BL32-related macros to marvell_def.h and fix BL32_LIMIT definition. Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Konstantin Porotchkin authored on 14 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	814ce2f Browse files » plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer ... The phy porting layer uses defaults defined in "phy-default-porting-layer.h" when board specific file "phy-porting-layer.h" is not found. Because of the regression the board specific directory was not included, therefore all boards used default parameters. Change-Id: I66e5e6eb8a39cca5aeeb4de6dab2ceddc39c1e31 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 28 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	ed84fe8 Browse files » plat: marvell: armada: configure amb for all CPs ... Before this patch the configuration took place only for CP0 and CP1, but since new platforms can contains up to 3 CPs update is required. Change-Id: Iebd50bbe7b9772063e2c4efb3a7ecbfd593e950d Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 12 Apr 2019 Marcin Wojtas committed on 19 Jun 2020
2020-06-06	32b3b99 Browse files » ddr: a80x0: add DDR 32-bit ECC mode support ... Change a topology map from internal database to SPD based for 32bit bus width mode Change-Id: I803166893ddc2fd916fc8a1c27fffd34b6ec0c72 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 10 Mar 2019 Marcin Wojtas committed on 6 Jun 2020
2020-06-06	85d2ed1 Browse files » ble: ap807: clean-up PLL configuration sequence ... Remove pll powerdown from pll configuration sequence to improve stability. Remove redundant cases, which no longer exist. Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200, which is not used by 806/807. Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 10 Feb 2019 Marcin Wojtas committed on 6 Jun 2020