/* * Copyright (C) 2016 NXP Semiconductors * * SPDX-License-Identifier: GPL-2.0 * * Refer docs/README.imxmage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage */ soc imx7 loadaddr 0x80000000 dcdofs 0x400 #include <mach/imx7-ddr-regs.h> wm 32 0x30340004 0x4F400005 wm 32 0x30391000 0x00000002 wm 32 MX7_DDRC_MSTR 0x03040008 wm 32 MX7_DDRC_RFSHTMG 0x00200038 wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 wm 32 MX7_DDRC_INIT0 0x00350001 wm 32 MX7_DDRC_INIT3 0x00c3000a wm 32 MX7_DDRC_INIT4 0x00010000 wm 32 MX7_DDRC_INIT5 0x00110006 wm 32 MX7_DDRC_RANKCTL 0x0000033f wm 32 MX7_DDRC_DRAMTMG0 0x0a0e110b wm 32 MX7_DDRC_DRAMTMG1 0x00020211 wm 32 MX7_DDRC_DRAMTMG2 0x03060708 wm 32 MX7_DDRC_DRAMTMG3 0x00a0500c wm 32 MX7_DDRC_DRAMTMG4 0x05020307 wm 32 MX7_DDRC_DRAMTMG5 0x02020404 wm 32 MX7_DDRC_DRAMTMG6 0x02020003 wm 32 MX7_DDRC_DRAMTMG7 0x00000202 wm 32 MX7_DDRC_DRAMTMG8 0x00000202 wm 32 MX7_DDRC_ZQCTL0 0x00600018 wm 32 MX7_DDRC_ZQCTL1 0x00e00100 wm 32 MX7_DDRC_DFITMG0 0x02098205 wm 32 MX7_DDRC_DFITMG1 0x00060303 wm 32 MX7_DDRC_DFIUPD0 0x80400003 wm 32 MX7_DDRC_DFIUPD1 0x00100020 wm 32 MX7_DDRC_DFIUPD2 0x80100004 wm 32 MX7_DDRC_ADDRMAP0 0x00000015 wm 32 MX7_DDRC_ADDRMAP1 0x00161616 wm 32 MX7_DDRC_ADDRMAP4 0x00000f0f wm 32 MX7_DDRC_ADDRMAP5 0x04040404 wm 32 MX7_DDRC_ADDRMAP6 0x0f0f0404 wm 32 MX7_DDRC_ODTCFG 0x06000600 wm 32 MX7_DDRC_ODTMAP 0x00000000 wm 32 0x30391000 0x00000000 wm 32 MX7_DDR_PHY_PHY_CON0 0x17421e40 wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 wm 32 MX7_DDR_PHY_PHY_CON2 0x00010000 wm 32 MX7_DDR_PHY_PHY_CON4 0x0007080c wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e wm 32 MX7_DDR_PHY_RODT_CON0 0x01010000 wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x06060606 wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x0a0a0a0a wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000008 wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000008 wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7306 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1 wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304 wm 32 0x30384130 0x00000000 wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 check 32 until_any_bit_set MX7_DDRC_STAT 0x1