ARM: at91: sama5d27-som1-ek: add barebox_update and multi environment support ...

We now have second stage support for running from sdmmc0 and sdmmc1.
Add a barebox environment and update handler for the two SD cards.

As fall back, we use the environment in the QSPI flash as before as this
is soldered to the SoM and is always available.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: populate $bootsource and $bootsource_instance ...

The BootROM passes us information about the boot medium in r4 and we
already use that in first stage and pass it along to second stage
PBL already. To make use of it, we need to pass it to barebox proper, do
this by writing it in the last 4 bytes of the SRAM. As second stage
always run in DRAM, this is safe to do.

We could also write to SRAM directly from first stage, but at91bootstrap
passes info in r4 as well for the sama5d3 boards, so we do it likewise
to maintain compatibility.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: read back memory size from DDRAM controller ...

We hard code memory size at three places:
 - In the configuration we use to initialize the DDRAM controller
 - In the minimal available size passed from PBL to barebox proper
 - In the device tree memory node override

Remove the two latter ones and replace them with code that reads the
size back from controller.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d27-som1: add additional first stage entry point ...

The BootROM constrains us to a 64K big first stage bootloader. Add a PBL
entry point for a xload barebox that sets up the minimum necessary to
load a FAT32 barebox.bin from the SD-Card.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: reduce UART setup boilerplate with new helpers ...

The sama5d2 can be fused for one of 9 preset UART iosets. This is then
used by the BootROM for printing the `RomBOOT' header and for the XMODEM
protocol implemented by the SAM-BA monitor. Add two new sama5d2 specific
helpers:

- sama5d2_dbgu_setup_ll for setting up the port with only pinmux and
  master clock as arguments
- sama5d2_resetup_uart_console for resetup of the uart console with
  same pinmux used by the ROM code

The default value, when unfused, is UART_1_IOSET_1 (RX@PD2, TX@PD3),
which are the same ones used on the two sama5d2 board supported so far.

With this change, the DEBUG_LL baudrate is also no longer fixed at 115200,
but instead comes from the CONFIG_BAUDRATE symbol.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: debug_ll: remove duplicated IS_ENABLED(CONFIG_DEBUG_LL) condition ...

There are three users of at91_dbgu_setup_ll and all already call this
function only when IS_ENABLED(CONFIG_DEBUG_LL). Remove the duplicated
condition from the function itself. This allows us to use the function
for pbl_set_console use later on, even with DEBUG_LL disabled.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: reuse stack set-up by first stage ...

Stack is always set up to end of SRAM before PBL, either by ROM code or
by first stage bootloader, be it at91bootstrap or barebox in a later
commit, so no need to change the stack pointer again.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add helpers for chain-loading barebox from SD-card ...

With PBL FAT support implemented, provide an sama5d2_sdhci_start_image
helper that can be called from the PBL to chainload a barebox.bin file
from the first FAT partition.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add code for sama5 boot source detection ...

SAMA5 BootROM passes information about the boot source in the r4
register. Add functions to parse these. To make use of this, entry point
must back up the r4 register, because otherwise it's clobbered by local
variable use.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: extend low level PMC driver for generic clk support ...

The SAMA5D2 and SAM9X60 both feature generic clocks, which we already
support in barebox proper, but not in PBL. Add PBL support for setting
the parent and enabling them, so we may use it to enable the SDMMC
peripherals in first stage.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add necessary Advanced Interrupt Controller configuration ...

Without reconfiguration of the AIC redirection, the OS interrupt
handling will misbehave later on. Add it to the SoC init.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add sama5d2 cache init ...

The L2 cache controller needs some initialization before use. Same goes
for the CAN SRAM, do so after the MMU setup.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: add sama5d2 matrix configuration ...

Different peripherals, including the SDRAM, are unusable without prior
matrix configuration. Port over the necessary at91bootstrap parts for
sama5d2 use.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: implement sama5d2 lowlevel init ...

Port over the low level initialization for sama5d2 SoCs from
at91bootstrap.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: watchdog: implement at91_wdt_disable ...

Board code might want to disable the watchdog in PBL and enable it later
prior to boot. Provide a helper to do so.

Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import low level DDRAMC initialization code from at91bootstrap ...

This commit imports DDRAMC initialization routines for use in PBL from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import early_udelay from at91bootstrap ...

For use by the incoming at91bootstrap DDRAMC initialization code,
this commit provides an early_udelay function usable in PBL imported from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_pit.c

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's at91_ddrsdrc.h ...

Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h

For easier comprehension, the replacement is done in three steps:
This last step copies the memory size querying functions from at91sam9_ddrsdr.h
to at91_ddrsdrc.h, then deletes it and fixes all references.

Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: migrate at91sam9_ddrsdr.h to use at91bootstrap's at91_ddrsdrc.h ...

Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h

For easier comprehension, the replacement is done in three steps:
Here the existing at91sam9_ddrsdr.h has its now duplicate (in function,
not name) macros removed and existing users are migrated to use the new
header.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: import at91bootstrap's at91_ddrsdrc.h ...

Instead of adding missing definitions to the existing at91sam9_ddrsdr.h
and adapting the incoming DDRAM initialization code from at91bootstrap,
just replace the lightly used existing header with:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/include/arch/at91_ddrsdrc.h

For easier comprehension, the replacement is done in three steps:
Here the header is imported.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: sama5d2: cast peripheral base addresses to __iomem pointers ...

The peripheral addresses should be always cast with IOMEM() anyway, so do
this directly in the header to make user code less verbose.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: remove <mach/hardware.h> include from assembly code ...

They are unused and force all headers included by it to have
__ASSEMBLY__ guards for non-preprocessor code. Avoid this.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: choose proper parent for both MCI clocks ...

When booting from SDMMC0, Use of SDMMC1 fails with:
ERROR: clk: couldn't set sdmmc1_gclk clk rate to 480000000 (-22), current rate: 32768

This is because the first stage bootloader only reparents the boot SDMMC
instance and barebox does no automatic reparenting for the other one.

Force both clocks to have a suitable parent.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: at91: add at91sam9/sama5 reset reason detection ...

The reset controller status register contains information about the last
reset's cause. Tell barebox about it.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: vexpress: dts: fix barebox partitioning breakage ...

There is no /smb@4000000 node upstream any longer as it was
renamed with the 8d158e1a4091 ("dts: update to v5.7-rc1") sync.

Adjust the barebox device tree accordingly. It's likely that this
resulted in barebox v2020.06.0 state, environment and update breakage on
the vexpress boards.

Cc: Roland Hieber <rhi@pengutronix.de>
Fixes: 8d158e1a4091 ("dts: update to v5.7-rc1")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: align all applicable memory nodes with spec and convention ...

The spec[1] says that top level memory nodes `shall have device_type =
"memory"'. Since 8226f7f9 ("of: base: parse all available memory nodes"),
we parse only nodes with device_type = "memory", so we should add the
device_type property where ever it's missing. When the nodes were first
added, this wasn't an issue because the skeleton.dtsi defined a memory
skeleton with correct device_type, but this was removed upstream and
imported into barebox along with 1dc748b3 ("dts: update to v5.1-rc1").

Upstream device trees with a memory node were adapted to have
device_type = "memory" in-line. This wasn't the case for nodes defined
only within barebox. Rectify this now and rename the nodes to feature a
unit name as well to be aligned with the upstream trend.

[1]: https://github.com/devicetree-org/devicetree-specification/releases/download/v0.3/devicetree-specification-v0.3.pdf

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: dts: fix now duplicate memory nodes ...

With the upstream migration to memory@BASE_ADDRESS naming scheme in the
device tree of some SoC families, we now have multiple overlapping memory
nodes in some of the barebox device trees. Rename the defunct overrides, so
they once again override the upstream nodes.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: i.MX50: fix renamed node reference ...

There is no /soc/aips@50000000 node upstream any longer as it was
renamed with the 8d158e1a4091 ("dts: update to v5.7-rc1") sync.

Adjust the barebox device tree accordingly. It's likely that this
resulted in barebox v2020.06.0 USB connectivity breakage for the
i.MX50's second USB PHY.

Fixes: 8d158e1a4091 ("dts: update to v5.7-rc1")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

ARM: rpi: dts: fix MMIO resources clash breaking boot ...

The rpi3b device tree specifies 1G of RAM in the memory node, but maps
the highest 16M of RAM's physical address range for peripheral use.

When support for device tree probing was first added for the rpi3b
in e8fab18835a1 ("ARM: rpi: switch to DT probe and multi-image build"),
it had a memory { } node overriding the kernel node size with 0, so the
size is computed later correctly.

1dc748b3b202 ("dts: update to v5.1-rc1") came and renamed the upstream
memory { } node to memory@0. So instead of overriding the old, we
now created a second dummy along with the broken node.
barebox did only parse the dummy, so it continued to limp along.

8226f7f90973 ("of: base: parse all available memory nodes") started
considering both nodes and rendered barebox v2020.05.0 unable to start
up on the rpi3b because of the conflict between RAM range and peripherals
like the bcm2835_mbox caused by parsing the broken memory node.

At least one board also was broken for the same reason[1], so a more
robust approach is in order. For nodes that lack a phandle, the
&{/path} syntax can be used instead. This has the benefit that should
the path disappear in future, a compile failure would result.

[1] 0d26ce1c11a1 ("ARM: Phytec phyFLEX i.MX6: delete wrong memory node")

Fixes: 1dc748b3b202 ("dts: update to v5.1-rc1")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

Merge branch 'for-next/spdx'