Cortex-A72: Implement workaround for erratum 859971

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LuminaSensum / arm-trusted-firmware

Browse code Cortex-A72: Implement workaround for erratum 859971 Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1 v2.0-rc0 v2.0 v1.6-rc1 v1.6-rc0 v1.6 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 v1.5
1 parent 45b52c2 commit 6de9b3364b458160c1229d00667caf93ba93c097 Eleanor Bonnici authored on 2 Aug 2017 Jeenu Viswambharan committed on 7 Sep 2017

Browse code

Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The
recommended workaround is to disable instruction prefetch.

Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1 v2.0-rc0 v2.0 v1.6-rc1 v1.6-rc0 v1.6 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 v1.5

1 parent 45b52c2 commit 6de9b3364b458160c1229d00667caf93ba93c097

Eleanor Bonnici authored on 2 Aug 2017

Jeenu Viswambharan committed on 7 Sep 2017

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Ignore Space Show notes View docs/cpu-specific-build-macros.rst

Ignore Space Show notes View include/lib/cpus/aarch32/cortex_a72.h

Ignore Space Show notes View include/lib/cpus/aarch64/cortex_a72.h

Ignore Space Show notes View lib/cpus/aarch32/cortex_a72.S

Ignore Space Show notes View lib/cpus/aarch64/cortex_a72.S

Ignore Space Show notes View lib/cpus/cpu-ops.mk

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