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2020-06-24	1367cc1 Browse files » Redirect security incident report to TrustedFirmware.org ... All projects under the TrustedFirmware.org project now use the same security incident process, therefore update the disclosure/vulnerability reporting information in the TF-A documentation. ------------------------------------------------------------------------ /!\ IMPORTANT /!\ Please note that the email address to send these reports to has changed. Please do not use trusted-firmware-security@arm.com anymore. Similarly, the PGP key provided to encrypt emails to the security email alias has changed as well. Please do not use the former one provided in the TF-A source tree. It is recommended to remove it from your keyring to avoid any mistake. Please use the new key provided on TrustedFirmware.org from now on. ------------------------------------------------------------------------ Change-Id: I14eb61017ab99182f1c45d1e156b96d5764934c1 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 24 Jun 2020
2020-06-23	ccf5863 Browse files » Merge changes Ifc34f2e9,Iefd58159 into integration ... * changes: Workaround for Cortex A76 erratum 1800710 Workaround for Cortex A76 erratum 1791580 Lauren Wehrmeister authored on 23 Jun 2020 TrustedFirmware Code Review committed on 23 Jun 2020
2020-06-23	ebd34be Browse files » doc: Add a binding document for COT descriptors ... Added a binding document for COT descriptors which is going to be used in order to create COT desciptors at run-time. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ic54519b0e16d145cd1609274a00b137a9194e8dd Manish V Badarkhe committed on 23 Jun 2020
2020-06-22	dcbfbcb Browse files » Workaround for Cortex A76 erratum 1800710 ... Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493 johpow01 committed on 22 Jun 2020
2020-06-22	d7b08e6 Browse files » Workaround for Cortex A76 erratum 1791580 ... Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925 johpow01 committed on 22 Jun 2020
2020-06-19	5a40d70 Browse files » drivers: marvell: add support for mapping the entire LLC to SRAM ... Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
2020-06-19	3768fec Browse files » TF-A: Add ARMv8.5 'bti' build option ... This patch adds BRANCH_PROTECTION = 4 'bti' build option which turns on branch target identification mechanism. Change-Id: I32464a6b51726a100519f449a95aea5331f0e82d Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 19 Jun 2020
2020-06-17	9935047 Browse files » Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration ... * changes: ddr: a80x0: add DDR 32-bit ECC mode support ble: ap807: improve PLL configuration sequence ble: ap807: clean-up PLL configuration sequence ddr: a80x0: add DDR 32-bit mode support plat: marvell: mci: perform mci link tuning for all mci interfaces plat: marvell: mci: use more meaningful name for mci link tuning plat: marvell: a8k: remove wrong or unnecessary comments plat: marvell: ap807: enable snoop filter for ap807 plat: marvell: ap807: update configuration space of each CP plat: marvell: ap807: use correct address for MCIx4 register plat: marvell: add support for PLL 2.2GHz mode plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic marvell: armada: add extra level in marvell platform hierarchy Manish Pandey authored on 17 Jun 2020 TrustedFirmware Code Review committed on 17 Jun 2020
2020-06-16	5eeb091 Browse files » Merge changes from topic "tegra194-ras-handling" into integration ... * changes: Tegra194: ras: verbose prints for SErrors Prevent RAS register access from lower ELs Tegra194: SiP: clear RAS corrected error records Tegra194: add RAS exception handling Manish Pandey authored on 16 Jun 2020 TrustedFirmware Code Review committed on 16 Jun 2020
2020-06-15	4f4fc18 Browse files » Add Raghu Krishnamurthy as a TF-A maintainer ... Change-Id: I3726f42f8f3de0cd88bd77a0f9d92a710649d18c Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 15 Jun 2020
2020-06-12	fbc44bd Browse files » Prevent RAS register access from lower ELs ... This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register accesses from EL1 or EL2 to EL3. RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438 Varun Wadekar committed on 12 Jun 2020
2020-06-09	10640d2 Browse files » Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration Madhukar Pappireddy authored on 9 Jun 2020 TrustedFirmware Code Review committed on 9 Jun 2020
	452d5e5 Browse files » plat/fvp: Add support for dynamic description of secure interrupts ... Using the fconf framework, the Group 0 and Group 1 secure interrupt descriptors are moved to device tree and retrieved in runtime. This feature is enabled by the build flag SEC_INT_DESC_IN_FCONF. Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 9 Jun 2020
	b4ad365 Browse files » GICv3: GIC-600: Detect GIC-600 at runtime ... The only difference between GIC-500 and GIC-600 relevant to TF-A is the differing power management sequence. A certain GIC implementation is detectable at runtime, for instance by checking the IIDR register. Let's add that test before initiating the GIC-600 specific sequence, so the code can be used on both GIC-600 and GIC-500 chips alike, without deciding on a GIC chip at compile time. This means that the GIC-500 "driver" is now redundant. To allow minimal platform support, add a switch to disable GIC-600 support. Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara authored on 25 Mar 2020 Madhukar Pappireddy committed on 9 Jun 2020
2020-06-06	57adbf3 Browse files » ddr: a80x0: add DDR 32-bit mode support ... This commit introduces 32-bit DDR topology map initialization. For that purpose a new DDR32 build flag is added, with according documentation update. Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 25 Feb 2019 Marcin Wojtas committed on 6 Jun 2020
2020-06-06	a284717 Browse files » marvell: armada: add extra level in marvell platform hierarchy ... This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Grzegorz Jaszczyk authored on 5 Nov 2019 Marcin Wojtas committed on 6 Jun 2020
2020-06-01	3f35709 Browse files » Rename Cortex-Hercules to Cortex-A78 ... Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson committed on 1 Jun 2020
2020-05-29	55d6596 Browse files » Add new maintainers for the project ... As per the trustedfirmware.org Project Maintenance Process [1], the current maintainers of the TF-A project have nominated some contributors to become maintainers themselves. List them in the maintainers.rst file to make this official. [1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ Change-Id: Id4e3cfd12a9074f4e255087fa5dd6fa5f902845f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 29 May 2020
2020-05-28	ac0b926 Browse files » Merge "doc: Update the list of code owners" into integration joanna.farley authored on 28 May 2020 TrustedFirmware Code Review committed on 28 May 2020
2020-05-28	da37ac8 Browse files » doc: Update the list of code owners ... Extend the list of modules and assign code owners to each of them. Change-Id: I267b87d8e239c7eff143b4c7e6ce9712fcf7101e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 28 May 2020
2020-05-27	f5c58af Browse files » plat/arm: Introduce TC0 platform ... This patch adds support for Total Compute (TC0) platform. It is an initial port and additional features are expected to be added later. TC0 has a SCP which brings the primary Cortex-A out of reset which starts executing BL1. TF-A optionally authenticates the SCP ram-fw available in FIP and makes it available for SCP to copy. Some of the major features included and tested in this platform port include TBBR, PSCI, MHUv2 and DVFS. Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif committed on 27 May 2020
2020-05-27	69be915 Browse files » Merge "plat: imx8mn: Add imx8mn basic support" into integration Sandrine Bailleux authored on 27 May 2020 TrustedFirmware Code Review committed on 27 May 2020
2020-05-26	1c301e7 Browse files » Merge "Cleanup the code for TBBR CoT descriptors" into integration Mark Dykes authored on 26 May 2020 TrustedFirmware Code Review committed on 26 May 2020
	a92d02d Browse files » Merge "doc: Fix plat_sdei_validate_entry_point() documentation" into integration Mark Dykes authored on 26 May 2020 TrustedFirmware Code Review committed on 26 May 2020
	b62a531 Browse files » doc: Fix plat_sdei_validate_entry_point() documentation ... Document the second argument of the function. Minor rewording. Change-Id: I190794b8cc74c99db4cfe6efc225217c32dd0774 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 26 May 2020
2020-05-25	00f8508 Browse files » doc: Fixes in PSA FF-A binding document ... - Fix possible run-time ELs value and xlat-granule size. - Remove mandatory field for stream-ids. - Define interrupts attributes to <u32>. - Remove mem-manage field. - Add description for memory/device region attributes. Co-authored-by: Manish Pandey <manish.pandey2@arm.com> Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I71cf4406c78eaf894fa6532f83467a6f4110b344 Louis Mayencourt authored on 8 Apr 2020 Olivier Deprez committed on 25 May 2020
2020-05-25	662af36 Browse files » SPCI is now called PSA FF-A ... SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA FF-A(in documents) or simply FFA(in code). Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760 Signed-off-by: J-Alves <joao.alves@arm.com> J-Alves authored on 7 May 2020 Olivier Deprez committed on 25 May 2020
2020-05-22	58fdd60 Browse files » plat: imx8mn: Add imx8mn basic support ... Add imx8mn basic support Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ibdfcc87700bfaf980e429f3a5fa08515218ae78d Jacky Bai committed on 22 May 2020
2020-05-19	6cac724 Browse files » Enable v8.6 WFE trap delays ... This patch enables the v8.6 extension to add a delay before WFE traps are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in plat/common/aarch64/plat_common.c that disables this feature by default but platform-specific code can override it when needed. The only hook provided sets the TWED fields in SCR_EL3, there are similar fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in lower ELs but these should be configured by code running at EL2 and/or EL1 depending on the platform configuration and is outside the scope of TF-A. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d johpow01 authored on 22 Apr 2020 John committed on 19 May 2020
2020-05-19	ad43c49 Browse files » Cleanup the code for TBBR CoT descriptors ... CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c and tbbr_cot_bl2.c respectively. Common CoT used across BL1 and BL2 are moved to tbbr_cot_common.c. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5 Manish V Badarkhe committed on 19 May 2020