Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration

Merge "cpus: denver: disable cycle counter when event counting is prohibited" into integration

cpus: denver: disable cycle counter when event counting is prohibited ...

The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the
PMCR_EL0 to be saved in non-secure context.

This patch disables cycle counter when event counting is prohibited
immediately on entering the secure world to avoid leaking useful
information about the PMU counters. The context saving code later
saves the value of PMCR_EL0 to the non-secure world context.

Verified with 'PMU Leakage' test suite.

 ******************************* Summary *******************************
 > Test suite 'PMU Leakage'
                                                                 Passed
 =================================
 Tests Skipped : 2
 Tests Passed  : 2
 Tests Failed  : 0
 Tests Crashed : 0
 Total tests   : 4
 =================================

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3675e2b99b44ed23d86e29a5af1b496e80324875

Merge changes from topic "sp_secure_boot" into integration ...

* changes:
  dualroot: add chain of trust for secure partitions
  sptool: append cert_tool arguments.
  cert_create: add SiP owned secure partitions support

Merge "plat/fvp: Add support for dynamic description of secure interrupts" into integration

plat/fvp: Add support for dynamic description of secure interrupts ...

Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime. This
feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.

Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

GICv3: GIC-600: Detect GIC-600 at runtime ...

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

dualroot: add chain of trust for secure partitions ...

A new certificate "sip-sp-cert" has been added for Silicon Provider(SiP)
owned Secure Partitions(SP). A similar support for Platform owned SP can
be added in future. The certificate is also protected against anti-
rollback using the trusted Non-Volatile counter.

To avoid deviating from TBBR spec, support for SP CoT is only provided
in dualroot.
Secure Partition content certificate is assigned image ID 31 and SP
images follows after it.

The CoT for secure partition look like below.
+------------------+       +-------------------+
| ROTPK/ROTPK Hash |------>| Trusted Key       |
+------------------+       | Certificate       |
                           | (Auth Image)      |
                          /+-------------------+
                         /                   |
                        /                    |
                       /                     |
                      /                      |
                     L                       v
+------------------+       +-------------------+
| Trusted World    |------>| SiP owned SPs     |
| Public Key       |       | Content Cert      |
+------------------+       | (Auth Image)      |
                        /   +-------------------+
                       /                      |
                      /                      v|
+------------------+ L     +-------------------+
| SP_PKG1 Hash     |------>| SP_PKG1           |
|                  |       | (Data Image)      |
+------------------+       +-------------------+
        .                           .
        .                           .
        .                           .
+------------------+       +-------------------+
| SP_PKG8 Hash     |------>| SP_PKG8           |
|                  |       | (Data Image)      |
+------------------+       +-------------------+

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia31546bac1327a3e0b5d37e8b99c808442d5e53f

Merge "plat/arm: do not include export header directly" into integration

Merge "rockchip: increase FDT buffer size" into integration

Merge changes from topic "fix-agilex-initialization" into integration ...

* changes:
  plat: intel: Additional instruction required to enable global timer
  plat: intel: Fix CCU initialization for Agilex
  plat: intel: Add FPGAINTF configuration to when configuring pinmux
  plat: intel: set DRVSEL and SMPLSEL for DWMMC
  plat: intel: Fix clock configuration bugs

plat: intel: Additional instruction required to enable global timer ...

There are additional instruction needed to enable the global timer.
This fixes the global timer initialization

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98

plat: intel: Fix CCU initialization for Agilex ...

The CCU initialization loop uses the wrong units, this fixes that. This
also fixes snoop filter register set bits should be used instead of
overwriting the register

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia15eeeae5569b00ad84120182170d353ee221b31

rockchip: increase FDT buffer size ...

The size of buffer currently used to store the FDT passed from U-Boot as
a platform parameter is not large enough to store some RK3399 device
trees. The largest RK3399 device tree currently in U-Boot (for the
Pinebook Pro) is about 70KB in size when passed to TF-A, so increase the
buffer size to 128K which gives some headroom for possibly larger FDTs
in future.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Change-Id: I414caf20683cd47c02ee470dfa988544f3809919

plat: intel: Add FPGAINTF configuration to when configuring pinmux ...

FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019

plat: intel: set DRVSEL and SMPLSEL for DWMMC ...

DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677

plat: intel: Fix clock configuration bugs ...

This fixes a few issues on the Agilex clock configuration:
- Set clock manager into boot mode before configuring clock
- Fix wrong divisor used when calculating vcocalib
- PLL sync configuration should be read and then written
- Wait PLL lock after PLL sync configuration is done
- Clear interrupt bits instead of set interrupt bits after configuration

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70

sptool: append cert_tool arguments. ...

To support secure boot of SP's update cert tool arguments while
generating sp_gen.mk which in turn is consumed by build system.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2293cee9b7c684c27d387aba18e0294c701fb1cc

cert_create: add SiP owned secure partitions support ...

Add support to generate certificate "sip-sp-cert" for Secure
Partitions(SP) owned by Silicon provider(SiP).
To avoid deviation from TBBR specification the support is only added for
dualroot CoT and not for TBBR CoT.

A single certificate file is generated containing hash of individual
packages. Maximum 8 secure partitions are supported.

Following new options added to cert_tool:
 --sip-sp-cert --> SiP owned Secure Partition Content Certificate
 --sp-pkg1 --> Secure Partition Package1 file
 --sp-pkg2
 .....
 --sp-pkg8

Trusted world key pair is used for signing.

Going forward, this feature can be extended for Platfrom owned
Partitions, if required.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia6dfbc1447cfb41b1fcbd12cf2bf7b88f409bd8d

plat/arm: do not include export header directly ...

As per "include/export/README", TF-A code should never include export
headers directly. Instead, it should include a wrapper header that
ensures the export header is included in the right manner.

"tbbr_img_def_exp.h" is directly included in TF-A code, this patch
replaces it with its  wrapper header "tbbr_img_def.h".

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I31c1a42e6a7bcac4c396bb17e8548567ecd8147d

Merge "ti: k3: common: Make UART number configurable" into integration

Merge "rockchip: rk3368: increase MAX_MMAP_REGIONS" into integration

rockchip: rk3368: increase MAX_MMAP_REGIONS ...

Current value is 16, count the MAP_REGION calls gets us at least 17,
so increase the max value to 20 to have a bit of a margin.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: I93d0324f3d483758366e758f8f663545d365e03f

Merge "xlat_tables_v2: add base table section name parameter for spm_mm" into integration

Merge "dts: stm32mp157c: fix etzpc node location in DTSI file" into integration

Merge "ti: k3: common: Implement stub system_off" into integration

Merge "Rename Cortex-Hercules to Cortex-A78" into integration

Merge "Rename Cortex Hercules Files to Cortex A78" into integration

dts: stm32mp157c: fix etzpc node location in DTSI file ...

Fix etzpc node location in stm32mp157c DTSI file as requested during the
patch review. The comment was addressed then fixup change discarded while
rebasing.

Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d
Fixes: 627298d4b655 ("dts: stm32mp157c: add etzpc node")
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Merge "qemu/qemu_sbsa: increase size to handle fdt" into integration