LuminaSensum/arm-trusted-firmware

Fork: 0

LuminaSensum / arm-trusted-firmware

2019-03-15	Unverified 1fbb682 Browse files » Merge pull request #1888 from jts-arm/zeus ... Introduce preliminary support for Neoverse Zeus Dimitris Papastamos authored on 15 Mar 2019 GitHub committed on 15 Mar 2019
	Unverified 136b9fa Browse files » Merge pull request #1889 from jts-arm/var4 ... Apply variant 4 mitigation for Neoverse N1 Dimitris Papastamos authored on 15 Mar 2019 GitHub committed on 15 Mar 2019
	Unverified d409c3e Browse files » Merge pull request #1890 from jts-arm/mbedtls ... Update documentation for mbed TLS v2.16 Dimitris Papastamos authored on 15 Mar 2019 GitHub committed on 15 Mar 2019
	Unverified accabf4 Browse files » Merge pull request #1891 from soby-mathew/sm/increase_fvp_stack ... fvp: Increase the size of the stack for FVP Dimitris Papastamos authored on 15 Mar 2019 GitHub committed on 15 Mar 2019
2019-03-14	01aa524 Browse files » fvp: Increase the size of the stack for FVP ... When RECLAIM_INIT_CODE is 1, the stack is used to contain the .text.init section. This is by default enable on FVP. Due to the size increase of the .text.init section, the stack had to be adjusted contain it. Change-Id: Ia392341970fb86c0426cf2229b1a7295453e2e32 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt authored on 13 Mar 2019 Soby Mathew committed on 14 Mar 2019
	62e2d97 Browse files » Update documentation for mbed TLS v2.16 ... Change-Id: I1854b5830dbd48e909a4ce1b931c13fb3e997600 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 14 Mar 2019
	a4546e8 Browse files » Introduce preliminary support for Neoverse Zeus ... Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 14 Mar 2019
	8074448 Browse files » Apply variant 4 mitigation for Neoverse N1 ... This patch applies the new MSR instruction to directly set the PSTATE.SSBS bit which controls speculative loads. This new instruction is available at Neoverse N1 core so it's utilised. Change-Id: Iee18a8b042c90fdb72d2b98f364dcfbb17510728 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 14 Mar 2019
2019-03-13	Unverified d7cf435 Browse files » Merge pull request #1859 from JackyBai/master ... refact the imx8m common code and add the imx8mm support Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified 620d983 Browse files » Merge pull request #1883 from ambroise-arm/av/a17-errata ... Apply workarounds for errata of Cortex-A17 Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	be10dcd Browse files » Cortex-A17: Implement workaround for errata 852423 ... Change-Id: I3a101e540f0b134ecf9a51fa3d7d8e3d0369b297 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 13 Mar 2019
	0b64c19 Browse files » Cortex-A17: Implement workaround for errata 852421 ... Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 13 Mar 2019
	Unverified ab15922 Browse files » Merge pull request #1884 from AlexeiFedorov/af/set_march_to_arch_minor ... Allow setting compiler's target architecture Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified b9d20d0 Browse files » Merge pull request #1882 from ambroise-arm/av/a15-errata ... Apply workarounds for errata of Cortex-A15 Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified 046c21c Browse files » Merge pull request #1881 from sandrine-bailleux-arm/sb/doc-fixes ... Minor doc fixes Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified 9d0ac83 Browse files » Merge pull request #1880 from lmayencourt/lm/pie ... PIE: fix linking with pie and binutils > 2.27 Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified b79239d Browse files » Merge pull request #1879 from pbeesley-arm/pb/todo-removal ... Pb/todo removal Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified c0ce16f Browse files » Merge pull request #1878 from jts-arm/sctlr ... Apply stricter speculative load restriction Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified c61a807 Browse files » Merge pull request #1874 from hadi-asyrafi/qspi_boot ... intel: QSPI boot enablement Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified 0976b34 Browse files » Merge pull request #1873 from hadi-asyrafi/driver_qspi ... intel: Add driver for QSPI Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified d0759c2 Browse files » Merge pull request #1843 from DavidPu/xlat_tables_v2_non_recursion ... Remove recursion from xlat_tables_v2 library Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified 77913d4 Browse files » Merge pull request #1858 from thloh85-intel/dwmmc_fixes ... drivers: synopsys: Fix synopsys MMC driver Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified eb9da9e Browse files » Merge pull request #1856 from masahisak/synquacer-scmi-support ... plat/synquacer: enable SCMI support Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	5f2c690 Browse files » Cortex-A15: Implement workaround for errata 827671 ... This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 13 Mar 2019
	75a1ada Browse files » Cortex-A15: Implement workaround for errata 816470 ... Change-Id: I9755252725be25bfd0147839d7df56888424ff84 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 13 Mar 2019
	Unverified e082009 Browse files » Merge pull request #1877 from bryanodonoghue/integration+bl2-el3-eret-fix-v2 ... bl2-el3: Fix exit to bl32 by ensuring full write to SPSR Dimitris Papastamos authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified 36a540d Browse files » Merge pull request #1861 from Yann-lms/checkpatch ... Update checkpatch options Dimitris Papastamos authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	Unverified 69905f7 Browse files » Merge pull request #1875 from Yann-lms/bsec ... fdts: stm32mp1: add bsec node Dimitris Papastamos authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
	520f864 Browse files » bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed ... A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to programming the lower-order 16 bits of the SPSR to populate into the CPSR on eret. The BL1 smc-handler code is identical and has the same shortfall in programming the SPSR from the platform defined struct entry_point_info->spsr. msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In order to ensure the 16 lower-order processor mode bits x->[15:8] and c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1. This change ensures we capture the x field, which we are interested in and not the f field which we are not. Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1') Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Bryan O'Donoghue committed on 13 Mar 2019
	eb20f04 Browse files » bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR ... Prior to entry into BL32 we set the SPSR by way of msr spsr, r1. This unfortunately only writes the bits f->[31:24] and c->[7:0]. This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0] fields of the SPSR. For the purposes of initial setup of the SPSR the x and c fields should be sufficient and importantly will capture the necessary lower-order control bits that f:c alone do not. This is important to do to ensure the SPSR is set to the mode the platform intends prior to performing an eret. Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image") Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Bryan O'Donoghue committed on 13 Mar 2019