2015-01-12 |
Juno: Add support for image overlaying in Trusted SRAM
...
This patch allows the BL3-1 NOBITS section to overlap the BL1 R/W
section since the former will always be used after the latter.
Similarly, the BL3-2 NOBITS section can overlay the BL2 image
when BL3-2 is loaded in Trusted SRAM.
Due to the current size of the images, there is no actual overlap.
Nevertheless, this reorganization may help to optimise the Trusted
SRAM usage when the images size grows.
Note that because BL3-1 NOBITS section is allowed to overlap the
BL1 R/W section, BL1 global variables will remain valid only until
execution reaches the BL3-1 entry point during a cold boot.
Documentation updated accordingly.
Fixes ARM-software/tf-issues#254
Change-Id: Id538f4d1c7f1f7858108280fd7b97e138572b879
Juan Castillo
committed
on 12 Jan 2015
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2014-12-10 |
Remove IRQ_SEC_SGI_8 constant
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In both FVP and Juno ports, IRQ #16, which is a PPI, is incorrectly
identified as secure SGI #8 through the constant IRQ_SEC_SGI_8.
This patch removes it.
Fixes ARM-software/tf-issues#282
Change-Id: I9e52d849611ffcd2b1f28e56dd156c5b217ed63e
Sandrine Bailleux
committed
on 10 Dec 2014
|
2014-11-11 |
Merge pull request #220 from soby-mathew/sm/reassign_crash_console
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Use the BL3-1 runtime console as the crash console.
danh-arm
committed
on 11 Nov 2014
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2014-11-04 |
Use the BL3-1 runtime console as the crash console.
...
This patch reassigns the crash console on Juno and FVP to use the runtime
BL3-1 console. The crash console is changed to SoC UART0 (UART2) from the
previous FPGA UART0 (UART0) on Juno. In FVP, it is changed from UART0 to
UART1.
Fixes ARM-software/tf-issues#256
Change-Id: I7df54f86ca00ec2652c27261dd66a94c12610816
Soby Mathew
committed
on 4 Nov 2014
|
Merge pull request #219 from jcastillo-arm/jc/tf-issues/253
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Improvements to ARM GIC driver
Juno: Use the generic ARM GIC driver
danh-arm
committed
on 4 Nov 2014
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2014-10-31 |
Juno: Use the generic ARM GIC driver
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This patch replaces the usage of the GIC private driver in Juno with
the generic ARM GIC driver. The private driver is no longer necessary
and has been removed from the Juno port.
Fixes ARM-software/tf-issues#253
Change-Id: I6aaabc252e5e6fb5fcf44ab6d0febd9b38791056
Juan Castillo
committed
on 31 Oct 2014
|
2014-10-29 |
Optimize Cortex-A57 cluster power down sequence on Juno
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This patch optimizes the Cortex-A57 cluster power down sequence by not
flushing the Level1 data cache. The L1 data cache and the L2 unified
cache are inclusive. A flush of the L2 by set/way flushes any dirty
lines from the L1 as well. This is a known safe deviation from the
Cortex-A57 TRM defined power down sequence. This optimization can be
enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build
flag. Each Cortex-A57 based platform must make its own decision on
whether to use the optimization.
This patch also renames the cpu-errata-workarounds.md to
cpu-specific-build-macros.md as this facilitates documentation
of both CPU Specific errata and CPU Specific Optimization
build macros.
Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
Soby Mathew
committed
on 29 Oct 2014
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2014-10-28 |
Merge pull request #217 from jcastillo-arm/jc/tf-issues/257
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FVP: keep shared data in Trusted SRAM
danh-arm
committed
on 28 Oct 2014
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Merge pull request #216 from vikramkanigiri/vk/juno_standby_support
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Juno: Support entry into a standby state
danh-arm
committed
on 28 Oct 2014
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2014-10-22 |
FVP: keep shared data in Trusted SRAM
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This patch deprecates the build option to relocate the shared data
into Trusted DRAM in FVP. After this change, shared data is always
located at the base of Trusted SRAM. This reduces the complexity
of the memory map and the number of combinations in the build
options.
Fixes ARM-software/tf-issues#257
Change-Id: I68426472567b9d8c6d22d8884cb816f6b61bcbd3
Juan Castillo
committed
on 22 Oct 2014
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2014-10-21 |
Juno: Support entry into a standby state
...
This patch adds support on the Juno platform for entering a wfi in
response to a PSCI CPU_SUSPEND call where the state type is a
standby state.
Change-Id: I0a102dee1f8d2ad936c63ad1d1d3ad001a4a4768
Vikram Kanigiri
committed
on 21 Oct 2014
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2014-10-14 |
Juno: Reserve some DDR-DRAM for secure use
...
This patch configures the TrustZone Controller in Juno to split
the 2GB DDR-DRAM memory at 0x80000000 into Secure and Non-Secure
regions:
- Secure DDR-DRAM: top 16 MB, except for the last 2 MB which are
used by the SCP for DDR retraining
- Non-Secure DDR-DRAM: remaining DRAM starting at base address
Build option PLAT_TSP_LOCATION selects the location of the secure
payload (BL3-2):
- 'tsram' : Trusted SRAM (default option)
- 'dram' : Secure region in the DDR-DRAM (set by the TrustZone
controller)
The MMU memory map has been updated to give BL2 permission to load
BL3-2 into the DDR-DRAM secure region.
Fixes ARM-software/tf-issues#233
Change-Id: I6843fc32ef90aadd3ea6ac4c7f314f8ecbd5d07b
Juan Castillo
committed
on 14 Oct 2014
|
2014-10-09 |
Juno: Use TZC-400 driver calls
...
This patch replaces direct accesses to the TZC-400 registers by the
appropiate calls to the generic driver available in the Trusted
Firmware in order to initialize the TrustZone Controller.
Functions related to the initialization of the secure memory,
like the TZC-400 configuration, have been moved to a new file
'plat_security.c'. This reorganization makes easier to set up
the secure memory from any BL stage.
TZC-400 initialization has been moved from BL1 to BL2 because BL1
does not access the non-secure memory. It is BL2's responsibility
to enable and configure the TZC-400 before loading the next BL
images.
In Juno, BL3-0 initializes some of the platform peripherals, like
the DDR controller. Thus, BL3-0 must be loaded before configuring
the TrustZone Controller. As a consequence, the IO layer
initialization has been moved to early platform initialization.
Fixes ARM-software/tf-issues#234
Change-Id: I83dde778f937ac8d2996f7377e871a2e77d9490e
Juan Castillo
committed
on 9 Oct 2014
|
2014-09-25 |
Merge pull request #214 from soby-mathew/sm/bl_specific_mmap
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Create BL stage specific translation tables
achingupta
committed
on 25 Sep 2014
|
Create BL stage specific translation tables
...
This patch uses the IMAGE_BL<x> constants to create translation tables specific
to a boot loader stage. This allows each stage to create mappings only for areas
in the memory map that it needs.
Fixes ARM-software/tf-issues#209
Change-Id: Ie4861407ddf9317f0fb890fc7575eaa88d0de51c
Soby Mathew
authored
on 3 Sep 2014
Achin Gupta
committed
on 25 Sep 2014
|
2014-09-22 |
Remove BSS section access by 'plat_print_gic' during crash reporting
...
This patch avoids the problem of crash reporting mechanism accessing
global data in BSS by 'plat_print_gic_regs' for FVP platforms. Earlier
it depended on the global 'plat_config' object for the GIC Base address
in FVP platforms which would have caused exception if it were accessed
before the BSS was initialized. It is now fixed by dynamically
querying the V2M_SYS_ID to find the FVP model type and accordingly
selecting the appropriate GIC Base address.
This patch also fixes the 'plat_print_gic_regs' to use the correct GIC
Distributor base address for printing GICD_IS_PENDR register values
for both Juno and FVP platforms.
Fixes ARM-Software/tf-issues#236
Change-Id: I545c7b908b3111419bf27db0575ce86acf86784b
Soby Mathew
committed
on 22 Sep 2014
|
2014-08-27 |
Miscellaneous documentation fixes
...
This patch gathers miscellaneous minor fixes to the documentation, and comments
in the source code.
Change-Id: I631e3dda5abafa2d90f464edaee069a1e58b751b
Co-Authored-By: Soby Mathew <soby.mathew@arm.com>
Co-Authored-By: Dan Handley <dan.handley@arm.com>
Sandrine Bailleux
authored
on 6 Aug 2014
Dan Handley
committed
on 27 Aug 2014
|
2014-08-21 |
Rationalize UART usage among different BL stages
...
This patch changes the UART port assignment for various BL stages
so as to make it consistent on the platform ports. The BL1, BL2 and
BL3-1 now uses UART0 on the FVP port and SoC UART0 on the Juno port.
The BL3-2 uses UART2 on the FVP port and FPGA UART0 on the Juno
port.
This provides an interim fix to ARM-software/tf-issues#220 until
support is added for changing the UART port for a BL image between
cold boot and runtime.
Change-Id: Iae5faea90be3d59e41e597b34a902f93e737505a
Soby Mathew
committed
on 21 Aug 2014
|
Juno: Read primary CPU MPID from SCC GPR_1
...
This patch removes the PRIMARY_CPU definition hardcoded in the
Juno port. Instead, the primary CPU is obtained at runtime by
reading the SCC General Purpose Register 1 (GPR_1), whose value
is copied by the SCP into shared memory during the boot process.
Change-Id: I3981daa92eb7142250712274cf7f655b219837f5
Juan Castillo
authored
on 12 Aug 2014
Soby Mathew
committed
on 21 Aug 2014
|
Juno: Implement PSCI SYSTEM_OFF and SYSTEM_RESET APIs
...
This patch adds the Juno platform specific handlers for PSCI
SYSTEM_OFF and SYSTEM_RESET operations.
Change-Id: Ie389adead533ec2314af44d721b4d0f306147c7d
Juan Castillo
authored
on 12 Aug 2014
Soby Mathew
committed
on 21 Aug 2014
|
Juno: Add support for Test Secure-EL1 Payload
...
This patch implements the TSP on Juno. It executes from on-chip Trusted
SRAM.
Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.
This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
- memory fragmentation is reduced enough to fit BL3-2 in;
- new base addresses are suitable for release builds as well as debug
ones;
- each image has a few extra kilobytes for future growth.
BL3-1 and BL3-2 are the images which received the biggest allocations
since they will most probably grow the most.
This patch also adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.
Change-Id: I1c5b51858700027ee283ac85d18e06863a27c72e
Sandrine Bailleux
authored
on 17 Jul 2014
Soby Mathew
committed
on 21 Aug 2014
|
Juno: Implement PSCI CPU_OFF and CPU_SUSPEND APIs
...
This patch adds support for PSCI CPU_OFF and CPU_SUSPEND APIs to the Juno port
of the ARM Trusted Firmware. The maximum affinity level that can be suspended is
the cluster level (affinity level 1). Support for suspending the system level is
not present.
Change-Id: Ie2c9da0acd7d1b0d5ac64940cdf40347153e52c8
Achin Gupta
authored
on 18 Aug 2014
Soby Mathew
committed
on 21 Aug 2014
|
Juno: Implement initial platform port
...
This patch adds the initial port of the ARM Trusted Firmware on the Juno
development platform. This port does not support a BL3-2 image or any PSCI APIs
apart from PSCI_VERSION and PSCI_CPU_ON. It enables workarounds for selected
Cortex-A57 (#806969 & #813420) errata and implements the workaround for a Juno
platform errata (Defect id 831273).
Change-Id: Ib3d92df3af53820cfbb2977582ed0d7abf6ef893
Sandrine Bailleux
authored
on 17 Jul 2014
Soby Mathew
committed
on 21 Aug 2014
|
2014-08-20 |
Add CPU specific power management operations
...
This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and
generic AEM sequences have been added. The latter is suitable for the
Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is
saved in the per-cpu data so that it can be easily accessed during power down
seqeunces.
An optional platform API has been introduced to allow a platform to disable the
Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak
definition of this function (plat_disable_acp()) does not take any action. It
should be overriden with a strong definition if the ACP is present on a
platform.
Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d
Soby Mathew
authored
on 14 Aug 2014
Dan Handley
committed
on 20 Aug 2014
|
Add platform API for reset handling
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This patch adds an optional platform API (plat_reset_handler) which allows the
platform to perform any actions immediately after a cold or warm reset
e.g. implement errata workarounds. The function is called with MMU and caches
turned off. This API is weakly defined and does nothing by default but can be
overriden by a platform with a strong definition.
Change-Id: Ib0acdccbd24bc756528a8bd647df21e8d59707ff
Soby Mathew
authored
on 14 Aug 2014
Dan Handley
committed
on 20 Aug 2014
|
Introduce framework for CPU specific operations
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This patch introduces a framework which will allow CPUs to perform
implementation defined actions after a CPU reset, during a CPU or cluster power
down, and when a crash occurs. CPU specific reset handlers have been implemented
in this patch. Other handlers will be implemented in subsequent patches.
Also moved cpu_helpers.S to the new directory lib/cpus/aarch64/.
Change-Id: I1ca1bade4d101d11a898fb30fea2669f9b37b956
Soby Mathew
authored
on 14 Aug 2014
Dan Handley
committed
on 20 Aug 2014
|
2014-08-19 |
Rework use of labels in assembly macros.
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This patch provides a workaround for the ASM_ASSERT label issue
and also reworks the use of labels in assembly macros.
If the caller of the ASM_ASSERT macro happened to use the
label '1' to jump past the ASM_ASSERT macro, it would not have
worked since the ASM_ASSERT macro internally used the same label.
Hence, as a workaround, this patch makes the label a high
number in the expectation that the caller will never use it.
Also updated the other assembly macros using numerical labels to
named lables.
Change-Id: Iec892359db84f2391ad2a83a92141c4d7049776a
Soby Mathew
committed
on 19 Aug 2014
|
fvp: Rework when platform actions are performed
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This patch reworks FVP port's power management implementation to perform
platform actions only when the platform exported hook is invoked for the highest
affinity level to enter/exit the OFF state.
For example, during a CPU_OFF operation, fvp_affinst_off() is called twice: for
affinity level 0 and affinity level 1 (in that order). CPU specific operations
are deferred until the next invocation if it is determined through a call to
psci_get_max_phys_off_afflvl() that this is CPU is the last in the cluster.
Similarly, during power up if the CPU is the first in the cluster, both CPU and
cluster specific operations are performed when fvp_affinst_on_finish() is
invoked for affinity level 1. Earlier, they were done across the two invocations
of the handler.
Change-Id: I4288ed3ba1385db36a69cc2e598deb219f209b8a
Achin Gupta
authored
on 31 Jul 2014
Soby Mathew
committed
on 19 Aug 2014
|
Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs
...
This patch adds support for SYSTEM_OFF and SYSTEM_RESET PSCI
operations. A platform should export handlers to complete the
requested operation. The FVP port exports fvp_system_off() and
fvp_system_reset() as an example.
If the SPD provides a power management hook for system off and
system reset, then the SPD is notified about the corresponding
operation so it can do some bookkeeping. The TSPD exports
tspd_system_off() and tspd_system_reset() for that purpose.
Versatile Express shutdown and reset methods have been removed
from the FDT as new PSCI sys_poweroff and sys_reset services
have been added. For those kernels that do not support yet these
PSCI services (i.e. GICv3 kernel), the original dtsi files have
been renamed to *-no_psci.dtsi.
Fixes ARM-software/tf-issues#218
Change-Id: Ic8a3bf801db979099ab7029162af041c4e8330c8
Juan Castillo
authored
on 12 Aug 2014
Dan Handley
committed
on 19 Aug 2014
|
Clarify platform porting interface to TSP
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* Move TSP platform porting functions to new file:
include/bl32/tsp/platform_tsp.h.
* Create new TSP_IRQ_SEC_PHY_TIMER definition for use by the generic
TSP interrupt handling code, instead of depending on the FVP
specific definition IRQ_SEC_PHY_TIMER.
* Rename TSP platform porting functions from bl32_* to tsp_*, and
definitions from BL32_* to TSP_*.
* Update generic TSP code to use new platform porting function names
and definitions.
* Update FVP port accordingly and move all TSP source files to:
plat/fvp/tsp/.
* Update porting guide with above changes.
Note: THIS CHANGE REQUIRES ALL PLATFORM PORTS OF THE TSP TO
BE UPDATED
Fixes ARM-software/tf-issues#167
Change-Id: Ic0ff8caf72aebb378d378193d2f017599fc6b78f
Dan Handley
committed
on 19 Aug 2014
|