LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-04-26	Unverified 45875d9 Browse files » fdts: Fix DTC warnings for STM32MP1 platform ... DTC issues below warnings for STM32MP1 platform for using upper case in unit address: fdts/stm32mp15-ddr.dtsi:8.20-151.5: Warning (simple_bus_reg): /soc/ddr@5A003000: simple-bus unit address format error, expected "5a003000" fdts/stm32mp157c-security.dtsi:9.25-13.5: Warning (simple_bus_reg): /soc/stgen@5C008000: simple-bus unit address format error, expected "5c008000" Fix this by using the lower case unit address for concerned nodes. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Change-Id: Id3d19ac3b47ec6bcea2bd3382225e2e923dc4a70 Manivannan Sadhasivam committed on 26 Apr 2019
	Unverified f657fa9 Browse files » docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable ... Since STM32MP1 platform supports different boards, it is necessary to build for a particular board. With the current instructions, the user has to modify the DTB_FILE_NAME variable in platform.mk for building for a particular board, but this can be avoided by passing the appropriate board DTB name via DTB_FILE_NAME make variable. Hence document the same in platform doc. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Change-Id: I16797e7256c7eb699a7b8846356fe430d0fe0aa1 Manivannan Sadhasivam committed on 26 Apr 2019
	Unverified cdf3d1a Browse files » stm32mp1: Add Avenger96 board support ... Add board support for Avenger96 board from Arrow Electronics. This board is based on STM32MP157A SoC and is one of the 96Boards Consumer Edition platform. More information about this board can be found in 96Boards website: https://www.96boards.org/product/avenger96/ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Change-Id: Ic905f26c38d03883c6e4ea221b4b275a4b534857 Manivannan Sadhasivam committed on 26 Apr 2019
2019-04-24	c3e4e08 Browse files » Merge changes from topic "av/console-register" into integration ... * changes: Console: Remove Arm console unregister on suspend Console: Allow to register multiple times Antonio Niño Díaz authored on 24 Apr 2019 TrustedFirmware Code Review committed on 24 Apr 2019
	5bec1e9 Browse files » Merge changes from topic "k3-sequence-fix" into integration ... * changes: ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID ti: k3: drivers: ti_sci: Cleanup sequence ID usage ti: k3: drivers: sec_proxy: Use direction definitions ti: k3: drivers: sec_proxy: Fix printf format specifiers Antonio Niño Díaz authored on 24 Apr 2019 TrustedFirmware Code Review committed on 24 Apr 2019
	568bfb7 Browse files » Merge changes from topic "k3-cleanups" into integration ... * changes: ti: k3: common: Align elements of map region table ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default ti: k3: common: Remove shared RAM space ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines Antonio Niño Díaz authored on 24 Apr 2019 TrustedFirmware Code Review committed on 24 Apr 2019
	c9ac30a Browse files » Console: Remove Arm console unregister on suspend ... Change-Id: Ie649b3c367a93db057eeaee7e83fa3e43f8c2607 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 24 Apr 2019
	71892ca Browse files » Console: Allow to register multiple times ... It removes the need to unregister the console on system suspend. Change-Id: Ic9311a242a4a9a778651f7e6380bd2fc0964b2ce Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 24 Apr 2019
2019-04-23	71a3527 Browse files » ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID ... When we get a sequence ID that does not match what we expect then the we are looking at is not the one we are expecting and so we error out. We can also assume this message is a stale message left in the queue, in this case we can read in the next message and check again for our message. Switch to doing that here. We only retry a set number of times so we don't lock the system if our message is actually lost and will never show up. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I6c8186ccc45e646d3ba9d431f7d4c451dcd70c5c Andrew F. Davis committed on 23 Apr 2019
	7a46903 Browse files » ti: k3: drivers: ti_sci: Cleanup sequence ID usage ... The sequence ID can be set with a message to identify it when it is responded to in the response queue. We assign each message a number and check for this same number to detect response mismatches. Start this at 0 and increase it by one for each message sent, even ones that do not request or wait for a response as one may still be delivered in some cases and we want to detect this. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I72b4d1ef98bf1c1409d9db9db074af8dfbcd83ea Andrew F. Davis committed on 23 Apr 2019
	fb98ca5 Browse files » ti: k3: drivers: sec_proxy: Use direction definitions ... The direction of a thread should be explicitly compared to avoid confusion. Also fixup message wording based on this direction. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ia3cf9413cd23af476bb5d2e6d70bee15234cbd11 Andrew F. Davis committed on 23 Apr 2019
	6c30bae Browse files » ti: k3: drivers: sec_proxy: Fix printf format specifiers ... The ID of a thread is not used outside for printing it out when something goes wrong. The specifier used is also not consistent. Instead of storing the thread ID, store its name and print that. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Id137c2f8dfdd5c599e220193344ece903f80af7b Andrew F. Davis committed on 23 Apr 2019
	d87af64 Browse files » Merge "Cortex A9: Fix typo in errata 794073 workaround" into integration Antonio Niño Díaz authored on 23 Apr 2019 TrustedFirmware Code Review committed on 23 Apr 2019
	217a3ed Browse files » Merge "Neoverse N1: Forces cacheable atomic to near" into integration Antonio Niño Díaz authored on 23 Apr 2019 TrustedFirmware Code Review committed on 23 Apr 2019
	932d029 Browse files » Merge changes from topic "yg/optee" into integration ... * changes: stm32mp1: add OP-TEE support stm32mp1: fix TZC400 configuration against non-secure DDR stm32mp1: remove useless define stm32mp: split stm32mp_io_setup function Antonio Niño Díaz authored on 23 Apr 2019 TrustedFirmware Code Review committed on 23 Apr 2019
	1989a19 Browse files » stm32mp1: add OP-TEE support ... Support booting OP-TEE as BL32 boot stage and secure runtime service. OP-TEE executes in internal RAM and uses a secure DDR area to store the pager pagestore. Memory mapping and TZC are configured accordingly prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where a header file describes the effective boot images. This change post processes header file content to get OP-TEE load addresses and set OP-TEE boot arguments. Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Yann Gautier committed on 23 Apr 2019
	eb4519e Browse files » stm32mp1: fix TZC400 configuration against non-secure DDR ... This change disables secure accesses to non-secure DDR which are useless. TF-A already maps non-secure memory with non-secure permissions thanks to the MMU. This change also corrects some inline comments. Change-Id: Id4c20c9ee5c95a666dae6b7446ed80baf2d53fb0 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Yann Gautier committed on 23 Apr 2019
	4d95bed Browse files » stm32mp1: remove useless define ... Remove STM32MP_DDR_SPEED_DFLT that is not used in STM32MP1 TF-A code. Change-Id: I780cdc4e93a8a9d997d50f67cfc582acd4a353d6 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 23 Apr 2019
	0b1aa77 Browse files » stm32mp: split stm32mp_io_setup function ... A new static function boot_mmc is created to simplify code maintenance of stm32mp_io_setup. Change-Id: I5c416e567e7e174fb1c2b435925a983c9c55fc40 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 23 Apr 2019
	7e8f52e Browse files » Merge changes from topic "aa-sbsa-watchdog" into integration ... * changes: plat/arm: introduce wrapper functions to setup secure watchdog drivers/sbsa: add sbsa watchdog driver Antonio Niño Díaz authored on 23 Apr 2019 TrustedFirmware Code Review committed on 23 Apr 2019
2019-04-19	883eab2 Browse files » ti: k3: common: Align elements of map region table ... This is only a formatting change but makes it instantly clear how each region is set. This is over 80 chars and the MT_RO are not strictly needed but this section very important to get right so make readability the priority here. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I2432deda05d4502b3478170296b5da43f26ad8e6 Andrew F. Davis committed on 19 Apr 2019
	e2dc40a Browse files » ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default ... This should be more secure and looks a bit cleaner. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ie5eaf0234b211ba02631cf5eab5faa1402a34461 Andrew F. Davis committed on 19 Apr 2019
	32e29fc Browse files » ti: k3: common: Remove shared RAM space ... We don't use this for anything right now, remove it. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I11505d01834f7ff1fdba46fda0acbb3b56fc9b66 Andrew F. Davis committed on 19 Apr 2019
	a481f8b Browse files » ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines ... This makes definitions more consistent, plus helps alignment. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I38fcdd76207586613d9934c9dc83d7a347e9e0fc Andrew F. Davis committed on 19 Apr 2019
2019-04-18	632ab3e Browse files » Neoverse N1: Forces cacheable atomic to near ... This patch forces all cacheable atomic instructions to be near, which improves performance in highly contended parallelized use-cases. Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 18 Apr 2019
2019-04-18	b4e9ab9 Browse files » Cortex A9: Fix typo in errata 794073 workaround ... Change-Id: I22568caf83b9846cd7b59241fcec34a395825399 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 18 Apr 2019
2019-04-17	b0c97da Browse files » plat/arm: introduce wrapper functions to setup secure watchdog ... The BL1 stage setup code for ARM platforms sets up the SP805 watchdog controller as the secure watchdog. But not all ARM platforms use SP805 as the secure watchdog controller. So introduce two new ARM platform code specific wrapper functions to start and stop the secure watchdog. These functions then replace the calls to SP805 driver in common BL1 setup code. All the ARM platforms implement these wrapper functions by either calling into SP805 driver or the SBSA watchdog driver. Change-Id: I1a9a11b124cf3fac2a84f22ca40acd440a441257 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Aditya Angadi committed on 17 Apr 2019
	f79abf5 Browse files » drivers/sbsa: add sbsa watchdog driver ... Add a driver for configuring the SBSA Generic Watchdog which aids in the detection of errant system behaviour. Change-Id: I5a1e7149c69fd8b85be7dfbcf511f431339946f4 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Aditya Angadi committed on 17 Apr 2019
	0e985d7 Browse files » DSU: Implement workaround for errata 798953 ... Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 17 Apr 2019
	2c3b76c Browse files » DSU: Small fix and reformat on errata framework ... Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 17 Apr 2019