tbbr/dualroot: Add fw_config image in chain of trust ...

fw_config image is authenticated using secure boot framework by
adding it into the single root and dual root chain of trust.

The COT for fw_config image looks as below:

+------------------+       +-------------------+
| ROTPK/ROTPK Hash |------>| Trusted Boot fw   |
+------------------+       | Certificate       |
                           | (Auth Image)      |
                          /+-------------------+
                         /                   |
                        /                    |
                       /                     |
                      /                      |
                     L                       v
+------------------+       +-------------------+
| fw_config hash   |------>| fw_config         |
|                  |       | (Data Image)      |
+------------------+       +-------------------+

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I08fc8ee95c29a95bb140c807dd06e772474c7367

cert_tool: Update cert_tool for fw_config image support ...

Updated cert_tool to add hash information of fw_config image into
the existing "trusted boot fw" certificate.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I720319225925806a2a9f50a1ac9c8a464be975f0

fiptool: Add fw_config in FIP ...

Added support in fiptool to include fw_config image
in FIP.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibbd14723a4141598d9d7f6bfcf88a0ef92cf87bc

plat/arm: Rentroduce tb_fw_config device tree ...

Moved BL2 configuration nodes from fw_config to newly
created tb_fw_config device tree.

fw_config device tree's main usage is to hold properties shared
across all BLx images.
An example is the "dtb-registry" node, which contains the
information about the other device tree configurations
(load-address, size).

Also, Updated load-address of tb_fw_config which is now located
after fw_config in SRAM.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic398c86a4d822dacd55b5e25fd41d4fe3888d79a

Merge changes Ifc34f2e9,Iefd58159 into integration ...

* changes:
  Workaround for Cortex A76 erratum 1800710
  Workaround for Cortex A76 erratum 1791580

Fix usage of incorrect function name ...

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Ic387630c096361ea9a963cde0018a0efb63e3bd2

Merge "FFA Version interface update" into integration

doc: Add a binding document for COT descriptors ...

Added a binding document for COT descriptors which is going
to be used in order to create COT desciptors at run-time.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ic54519b0e16d145cd1609274a00b137a9194e8dd

FFA Version interface update ...

Change handler of FFA version interface:
- Return SPMD's version if the origin of the call is secure;
- Return SPMC's version if origin is non-secure.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I0d1554da79b72b1e02da6cc363a2288119c32f44

stm32mp1: SP_MIN embeds Arm Architecture services ...

Embed Arch Architecture SMCCC services in stm32mp1 SP_MIN. This
service is needed by Linux kernel to setup the SMCCC conduit
used by its SCMI SMC transport driver.

Change-Id: I454a7ef3048a77ab73fff945e8115b60445d5841
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

stm32mp1: use last page of SYSRAM as SCMI shared memory ...

SCMI shared memory is used to exchange message payloads between
secure SCMI services and non-secure SCMI agents. It is mapped
uncached (device) mainly to conform to existing support in
the Linux kernel. Note that executive messages are mostly short
(few 32bit words) hence not using cache will not penalize much
performances.

Platform stm32mp1 shall configure ETZPC to harden properly the
secure and non-secure areas of the SYSRAM address space, that before
CPU accesses the shared memory when mapped non-secure.

This change defines STM32MP_SEC_SYSRAM_BASE/STM32MP_SEC_SYSRAM_SIZE and
STM32MP_NS_SYSRAM_BASE/STM32MP_NS_SYSRAM_SIZE.

Change-Id: I71ff02a359b9668ae1c5a71b5f102cf3d310f289
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: check stronger the secondary CPU entry point ...

When using SP_min as monitor, only sp_min_warm_entrypoint() is a valid
secure entry point.

Change-Id: I440cec798e901b11a34dd482c33b2e378a8328ab
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>

stm32mp1: disable neon in sp_min ...

Disable use of Neon VFP support for platform stm32mp1 when
building with SP_MIN runtime services as these can conflict with
non-secure world use of NEON support. This is preferred over a
systematic backup/restore of NEON context when switching
between non-secure and secure worlds.

When NEON support is disabled, this is done for both BL2 and BL32 as
build process uses common libraries built once for both binaries.

Change-Id: I4e8808dcb6ef58fc839e6f85fd6e45cfbaa34be0
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Workaround for Cortex A76 erratum 1800710 ...

Cortex A76 erratum 1800710 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core.  The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.

This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493

Workaround for Cortex A76 erratum 1791580 ...

Cortex A76 erratum 1791580 is a Cat B erratum present in earlier
revisions of the Cortex A76. The workaround is to set a bit in the
implementation defined CPUACTLR2 register, which forces atomic store
operations to write-back memory to be performed in the L1 data cache.

This errata is explained in this SDEN:
https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925

Merge changes from topic "tegra-memctrlv2-vpr-resize-bugfix" into integration ...

* changes:
  Tegra: sanity check NS address and size before use
  Tegra: memctrl_v2: fixup sequence to resize video memory

Merge "TF-A GIC driver: Add barrier before eoi" into integration

Merge "TF-A: Add ARMv8.5 'bti' build option" into integration

Merge changes from topic "scmi-msg" into integration ...

* changes:
  drivers/scmi-msg: smt entry points for incoming messages
  drivers/scmi-msg: support for reset domain protocol
  drivers/scmi-msg: support for clock protocol
  drivers/scmi-msg: driver for processing scmi messages

Merge "Fix typo in file Header guard" into integration

TF-A GIC driver: Add barrier before eoi ...

It is desired to have the peripheral writes completed to clear the
interrupt condition and de-assert the interrupt request to GIC before
EOI write. Failing which spurious interrupt will occurred.

A barrier is needed to ensure peripheral register write transfers are
complete before EOI is done.

GICv2 memory mapped DEVICE nGnR(n)E writes are ordered from core point
of view. However these writes may pass over different interconnects,
bridges, buffers leaving some rare chances for the actual write to
complete out of order.

GICv3 ICC EOI system register writes have no ordering against nGnR(n)E
memory writes as they are over different interfaces.

Hence a dsb can ensure from core no writes are issued before the previous
writes are *complete*.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: Ie6362009e2f91955be99dca8ece14ade7b4811d6

Merge "Tegra: introduce support for GICv3" into integration

Fix typo in file Header guard ...

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Change-Id: Iaf6deaeee2069720518221157edbb052bc42850a

Tegra: sanity check NS address and size before use ...

This patch updates the 'bl31_check_ns_address()' helper function to
check that the memory address and size passed by the NS world are not
zero.

The helper fucntion also returns the error code as soon as it detects
inconsistencies, to avoid multiple error paths from kicking in for the
same input parameters.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Change-Id: I46264f913954614bedcbde12e47ea0c70cd19be0

plat: marvell: armada: a8k: add OP-TEE OS MMU tables ...

Adjust the latest OP-TEE memory definitions to the
newest TF-A baseline.

Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

drivers: marvell: add support for mapping the entire LLC to SRAM ...

Add llc_sram_enable() and llc_sram_disable() APIs to Marvell
cache_lls driver.
Add LLC_SRAM definition to Marvell common makefile - disabled
by the default.
Add description of LLC_SRAM flag to the build documentation.

Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms ...

Extend the CCU tables with secure SRAM window in all board
setups that uses SoCs based on AP806/AP807 North Bridges

Change-Id: I4dc315e4ea847562ac8648d8a8739244b548c70e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: marvell: armada: reduce memory size reserved for FIP image ...

It is not needed to reserve 64MB for FIP. Limit this to 4MB
for both supported Armada SoC families.

Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Extract from bigger commit]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

plat: marvell: armada: platform definitions cleanup ...

- Remove
    TRUSTED_DRAM_BASE
    TRUSTED_DRAM_SIZE
    MARVELL_TRUSTED_SRAM_BASE
- Rename
    PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_*
    PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_*
    MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM
- Move
    MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h
- Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map
- Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM
- Add minor style improvents

Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[Improve patch after rebase]
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

plat: marvell: armada: a8k: check CCU window state before loading MSS BL2 ...

Make sure the current CCU window is not in use before adding
a new address map during MSS BL2 image load preparations.
At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is
added to MSS BL2 stage initialization, the DDR entry will be destroyed
and lead to the system hang.

Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>